Sr. Principal Design Engineer

Posted Yesterday
Be an Early Applicant
Austin, TX
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The successful applicant will be responsible for designing and developing high-performance, low-power Network on Chip products, focusing on hardware architecture, micro-architecture definition, and RTL design.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Successful applicant will participate in the design and development of a fully configurable and fully featured Network on Chip (NoC) product. Responsibilities include hardware architecture and micro-architecture definition, as well as RTL design to achieve high performance and low power. Familiarity with NoC technology and concepts, AMBA protocols (AXI, AHB, APB) as well as coherency protocols (ACE, CHI) required.

BSEE and at least 7 years of prior experience required. MSEE and at-least 5 years of prior experience strongly preferred.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Rtl
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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