Sr. Digital Implementation Engineer

Posted 24 Days Ago
Be an Early Applicant
Irvine, CA
Senior level
Information Technology • Semiconductor
The Role
As a Sr. Digital Implementation Engineer, you will create turn-key solutions for Cellular IoT devices, overseeing netlist delivery and ensuring the integrity of the RTL database. Responsibilities include defining synthesis methodology, running synthesis flows, and interfacing with physical design teams for timing closure.
Summary Generated by Built In

Alif Semiconductor is revolutionizing the way secure connected AI-enabled embedded solutions are created. We are looking for motivated individuals who want to be involved in a fast-paced environment with cutting-edge technology.


You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).

Additional Responsibilities

  • Run complete synthesis flow 
  • Define and document synthesis (including DFT insertion) methodology and scripts/flows 
  • UPF flow for defining power intent (at block and chip level) 
  • RTL and Netlist hand-off checks (LEC) 
  • Interface with Physical Design for floor-planning and timing closure 
  • Assist with design partitioning and floorplan. 
  • Analyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teams

Required Qualifications

  • Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure 
  • Familiarity with DFT (Tessent) and back-end (Cadence) tools Hands-on experience with digital logic synthesis for power and area optimization 
  • Experience in low power design issues, tools, and methodology including UPF power intent specification 
  • Proficient in Verilog/SV/Tcl/Perl/Python 
  • Highly motivated to debug and resolve CAD tool flow issues 
  • Self-starter with good analytical, problem solving and communication skills 
  • Bachelor’s degree in Electrical Engineering, a related discipline, or equivalent experience.

Preferred Qualifications

  • Strong expertise with Design Compiler or Genus. 
  • Experience with IP integration 
  • Experience with Synthesis, LEC, DFT, BIST 
  • Experience with Cadence Timing and ECO Flow 
  • Experience with Clock Domain Crossing (CDC) Analysis 
  • Experience with timing corner selection and library models
  • Proven track record of successful deep submicron technology node tapeout (including Silicon bring-up) 
  • Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT) 

Alif Semiconductor provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.

 

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.

Top Skills

Verilog,Systemverilog,Tcl,Perl,Python
The Company
157 Employees
On-site Workplace
Year Founded: 2019

What We Do

Alif Semiconductor is the industry-leading supplier of the next-generation Ensemble family of microcontrollers and fusion processors. The Ensemble family scales from single core MCUs to a new class of multi-core devices, fusion processors, that blend up to two Cortex-M55 MCU cores, up to two Cortex-A32 microprocessor cores capable of running high-level operating systems, and up to two Ethos-U55 microNPUs for AI/ML acceleration. With multi-layered security, scalable performance, and next-level integration, Alif MCUs and MPUs provide a wide range of functionalities on a single monolithic die. The Alif Ensemble family delivers increased AI/ML efficiency, lowers power consumption, and keeps data safe, all while offering a scalable processor continuum

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