Software Engineer II

Posted 3 Hours Ago
Be an Early Applicant
Pittsburgh, PA
Junior
Cloud • Hardware • Software • Semiconductor
The Role
As a Software Engineer II at Cadence, you will work on the Stratus High Level Synthesis product, responsible for maintaining and developing complex C++ code, implementing algorithms, and understanding hardware implications while collaborating with team members to enhance the software.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Are you ready to join the team that is changing the way the world does chip design? Today’s chips and systems are becoming too complex to continue design with the traditional RTL design techniques so the industry is moving to a higher level of design abstraction using SystemC and High Level Synthesis.

The Stratus High Level Synthesis (HLS) product from Cadence synthesizes SystemC input models into high quality Verilog RTL based on a target technology library and user constraints. Stratus is already in production flows at many of the industry’s top semiconductor and systems companies.

In this role, you will be responsible for the design, implementation and maintenance of one of the many complex phases of the Stratus synthesis process. This includes implementing in C++ many modern algorithms, design and implementation of complex data structures and understanding the hardware implications of C++ synthesis.

Come join our experienced team of outstanding software and hardware developers!

Role: Software Engineer II

Location: Pittsburgh, PA

Responsibilities:

  • Own, develop and maintain a portion of the Stratus C++ code base
  • Absorb requirements specifications for new features and write accompanying function specifications for the development process
  • Work closely with team members to develop techniques to increase the capability, capacity and stability of Stratus
  • Interface with regression system to test code commits as part of the development process

Position Requirements:

  • BS in CS or EE (or equivalent science) or 1 year of equivalent experience
  • MS in CS or EE (or equivalent science)

Additional Qualifications:

  • Good working knowledge of Modern C++ software design
  • Strong understanding of software data structures and algorithms
  • Basic understanding of the Verilog RTL design process
  • Hardware, especially VLSI, design a plus
  • Scripting language skills in Perl, Python or TCL a plus
  • Excellent written and oral communication skills
  • Team player. Responds to input from others and willing to speak up when help or information is needed

A Great Place to Do Great Work

Employees join Cadence because of our innovation and stay because of our culture. Working at Cadence means working alongside the industry’s brightest people and innovating for some of the biggest companies around the globe. Our employees feel empowered and supported to make their mark on the future of technology.

https://www.cadence.com/content/cadence-www/global/en_US/home/company/culture.html

We’re doing work that matters. Help us solve what others can’t.

Top Skills

C++
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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