Senior Staff Engineer, Digital IC Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Connectivity BU develops industry leading PAM4 optical digital signal processors (DSPs) power the optical interconnects inside the world’s cloud and AI data centers, and support both Ethernet and InfiniBand architectures. With increasing demands for training, inference and cloud computing, operators must quickly scale out their networks with reliable, low-latency, high-bandwidth connectivity. Marvell PAM4 DSPs deliver the performance and versatility needed to support AI and cloud frontend and backend networks at 1.6T, 800G, 400G, 200G and 100G

What You Can Expect

• As ASIC design engineer you will be responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs.
• Develop ASIC specification and micro-architecture of signal processing and communications algorithms.
• Analyze DSP challenges and opportunities, explore and compare different optimization directions, and generate trade-off curves for performance and cost (complexity/power/area/design time)
• Work on high-efficiency DSP design
• Design RTL for various PHY transceivers with data rates from 25Gbps to 224Gbps for diverse applications.
• Collaborate with Analog, Digital Verification, Firmware, and Application Engineering teams to deliver competitive PHY transceiver solutions across all product lines.
• Participate in various aspects of chip design RTL development, functional verification, RTL lint, cross clock domain (CDC) analysis, synthesis, formal equivalence, static timing analysis and PPA analysis.
• Post-silicon debug and correlation

What We're Looking For

• Strong experience in high speed DSP/FEC (Forward Error Correction)
• Hands on experience with matching DSP block model functionality to RTL's, synthesis, static timing analysis and functional verification
• Strong system level modeling, debugging and troubleshooting
• Strong language user in Matlab, Verilog, System Verilog, Perl, Unix Shell.
• Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
• Experience in both RTL development (block and subsystem level) and gate level verification and debug.
• Understanding of Design-for-Test (DFT) concepts, including Scan and BIST
• Experience with chip bring up and functional validation of the product in the lab
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
• Strong communication skills and effective team collaboration abilities
• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related fields with 5+ years of relevant experience, or a Master’s/PhD with 2+ years of relevant experience.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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