The role involves leading a software team on embedded C firmware projects, from architecture and development through to production. Responsibilities include debugging complex hardware issues, collaborating with cross-functional teams, and mentoring junior engineers. The position also entails developing software components for DSP products and ensuring successful product milestones.

The Director of Hardware Emulation will lead a technical team responsible for defining emulation strategy, developing test plans, and executing verification for large CCS product emulations. Responsibilities include interfacing with stakeholders for hardware requirements, optimizing validation environments, and automating emulation processes.

The Director of SOC Design will lead a team responsible for designing and integrating complex SOCs. Responsibilities include architecting designs, managing project timelines, guiding verification processes, and ensuring high quality in design outputs. The role involves collaboration with various teams and third-party vendors, along with mentoring talent within the organization.

As a Package Design Engineer, you will evaluate design feasibility based on package topology and requirements, implement physical designs, collaborate with simulation and operations teams, and manage layout-related tasks. Experience with flip chip packages and Cadence APD is preferred.

The Senior Manager of Talent Acquisition for Marvell will oversee recruitment strategies in the APAC region, ensuring efficiency and compliance while fostering partnerships with hiring managers. This role requires leading a recruitment team and collaborating with various stakeholders to fulfill talent needs, promoting diversity and inclusion throughout the recruitment process.

As a staff engineer in analog layout, you will develop next-generation high-speed SerDes IPs while working with finFET technologies. Responsibilities include full-custom circuit layout, verification and RC extraction, with an understanding of advanced semiconductor technology, design methodologies, and collaboration with global teams.

As a Senior Engineer in DFT Engineering, you will own the DFT design and verification process from setup to silicon bring up, support integration and enhancements in design flow, and work with advanced DFT techniques.

The Senior Sales Manager will develop and maintain account relationships, achieve sales objectives, implement strategies, and lead a sales team. This role focuses on building customer relationships in large accounts and driving team performance within a matrixed organization.

As a Senior Staff Hardware Design Engineer at Marvell, you'll design high-speed PCBs and oversee schematic designs, PCB layout, and performance analysis. You'll manage component procurement, board testing, and collaborate across teams to meet technical objectives.

The Analog Designer Intern will design, simulate, and verify analog blocks for optical transceivers, test existing designs, and collaborate with layout engineers for implementation. Responsibilities involve system-level modeling and addressing technical challenges in high-speed data transfer designs.

The role involves developing and qualifying SONiC based Platform for Marvell Packet Processors targeted for Data Centers. The engineer will handle complex routing and switching software, work with network programming languages, and manage high complex switching/routing infrastructure while collaborating with various teams on customer requirements.

As a Senior Staff Test Engineer, you'll develop test programs for characterization and production on Advantest 93K and Teradyne UltraFLEX platforms. You'll create detailed test documentation, engage with DFT/DFM teams for yield enhancement, convert test patterns to ATE format, and optimize test flows in a collaborative environment.

As a Senior Staff Design Verification Engineer, you will develop and maintain the verification environment using UVM, validate designs through rigorous test plans, debug failures, and ensure coverage targets are achieved while collaborating with design teams.

The Principal Firmware Engineer will develop embedded firmware for high-speed transceivers, implement DSP algorithms, develop protocols based on industry standards, and work in a fast-paced, team-oriented environment focusing on system level firmware and API/GUI development.

Lead and oversee all aspects of chip-level physical design including Place and Route activities. Conduct detailed analyses for timing, power, and signal integrity signoff. Manage physical verification tasks and collaborate with cross-functional teams to ensure successful project implementations. Mentor junior engineers and contribute to the development of design methodologies.

As a Senior Staff Timing Engineer, you will lead ASIC timing activities focusing on post RTL design, including synthesis, timing closure, and DFT generation. Collaborate with Analog/Digital design teams, improve methodologies, and support product teams throughout pre and post-silicon phases.

The role involves developing test plans for verification based on architectural specifications, creating testbench components in various programming languages, debugging test failures, analyzing coverage, and writing automation scripts. The position also includes conducting design and verification reviews with the engineering team.

As a System Hardware Engineer Intern, you will contribute to Marvell's Digital Signal Processing architecture team by developing and implementing algorithms for advanced communication systems, including adaptive equalizers and error correcting codes, and applying machine learning techniques.

The role entails owning the egress processor IP design, collaborating with architecture for feature enhancement, implementing specifications using RTL coding, ensuring quality criteria are met, and coordinating with physical design and verification teams for ASIC design and pre-silicon verification tasks.

Lead the development of high-speed, high-performance SerDes in advanced technology nodes. Collaborate with design teams, guide layout engineers, support IP characterization and validation, and assist in product and customer support.