Marvell Technology
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The Emulation Engineer will modify RTL to create emulation-friendly wrappers and enhance compile/run times using scripts. They will work on AI-enabling server chipsets and be responsible for the transition of RTL into emulation platforms.
The Analog Design Engineer will design circuits for high-speed optical transceivers, analyze specifications, supervise layout activities, validate performance models, collaborate across teams, and mentor junior engineers. The role emphasizes innovation in advanced CMOS nodes and multi-GHz analog design.
As an Analog IC Design Principal Engineer, you'll design sophisticated CMOS transceiver/SERDES products. Responsibilities include circuit architecture and implementation for components like PLL, DLL, ADC, and regulators. You'll also perform design verification using SPICE and MATLAB, supervise layout activities, and collaborate on test verification and document generation.
As a Cyber Threat Hunting and Intelligence Analyst at Marvell, you will identify and respond to cyber threats, develop detection logic and response playbooks, produce threat reports, and collaborate with the SOC and CSIRT teams to enhance threat detection and response capabilities.
The role involves leading a team of analog design engineers in designing CMOS transceiver, PLL, DLL, ADC, and amplifiers. Responsibilities include architectural investigation, design verification using industry-standard tools, interfacing with layout and application teams, and managing analog IP delivery from concept to production.
Develop power solutions for Marvell devices, evaluate designs for electrical performance, collaborate with layout engineers, and perform simulations for efficiency. Require expertise in power integrity, PDN design, and knowledge of circuit elements.
Work as a Staff Design Verification Engineer at Marvell, responsible for verifying RTL engineers' designs, running simulations, debugging, and presenting test plans. Requires Bachelor's or Master's degree in Computer Science or Electrical Engineering with 3-5 years of experience.
Lead a team of ASIC design engineers in developing cutting-edge IP, subsystems, and SOCs for data center, wireless, and automotive applications. Manage project timelines, collaborate with cross-functional teams, drive technology innovation, ensure quality assurance, and engage with vendors and stakeholders.
The Principal Engineering Program Manager at Marvell will lead complex product development efforts in semiconductor solutions, managing projects from planning to production release, and ensuring communication and problem resolution among cross-functional teams. They will identify risks and drive execution to meet program goals.
The Analog IC Design Engineer will work on high-speed Ethernet product development, defining specifications, schematics, and drive designs into production. Responsibilities include collaborating on mask design and ensuring customer satisfaction with the final products.
As an Analog Layout Junior Engineer, you will produce designs from schematics provided by designers, using CAD tools to create implementation layers and conduct verifications with Cadence Virtuoso. You will collaborate with global teams to refine designs and will engage in communication and presentations regarding project updates and challenges.
As a Principal Analog IC Design Engineer at Marvell, you will design sophisticated CMOS transceiver and SERDES products, focusing on the implementation and verification of complex circuits like PLL, DLL, ADC, and amplifiers. Your role includes ensuring performance targets are met and conducting design verification using industry-standard tools. You will leverage your expertise in mixed-signal design and high-speed digital circuits.
As an Analog Layout Engineer, you will work with Analog IC Designers to create and refine layout designs using CAD tools. You will simulate and verify designs, collaborate closely with your designer partner, and communicate progress to various teams. The role involves learning and applying electrical concepts while developing innovative technologies.
Principal SW/FW Engineer at Marvell working on optical communication products. Responsibilities include developing embedded FW, C SDK, Python-based GUI, and automated regression infrastructure for products.
The Staff Engineer in Analog Layout will design and optimize analog mixed-signal layouts, work with circuit designers to meet specifications, and ensure that layouts comply with design rules. Responsibilities include floor planning, custom layout, verification, and maintaining documentation of methodologies and decisions.
The Analog Mixed Signal Design Engineer will work with a team on architectural investigations and implementation of circuits like PLL, DLL, ADC, and regulators. Responsibilities include design verification using tools like SPICE and Spectre while collaborating with layout and verification teams, and managing the delivery of analog IP from concept to production.
The Principal Analog Mixed Signal Design Engineer will work on designing high-speed and optical transceivers, focusing on circuits like PLLs, DLLs, ADCs, and amplifiers. Responsibilities include ensuring performance targets, design verification using tools like SPICE and MATLAB, and managing the delivery of analog IP from concept to production, collaborating with layout and verification teams.
The role involves architectural investigations and implementation of circuits like PLL, DLL, ADC, and amplifiers, ensuring performance targets are met. The candidate will design and verify analog IP and interface with various teams to bring designs from concept to production.
The Principal Engineer, Reliability will oversee new product qualification of semiconductor products, conduct reliability stress testing, and collaborate with internal and external partners on project execution. Responsibilities include data analysis, managing multiple qualifications, and developing monitoring programs to enhance product reliability.
The Analog Design Engineer, Principal will analyze design specifications, create and supervise transistor-level analog designs for multi-GHz applications, ensure post-layout verification, model and validate analog performance, and mentor junior designers while collaborating with cross-functional teams.