Search the 187 jobs at Marvell Technology

As an Analog Designer Intern, you will work with the Optical Digital Signal Processing group to design and validate circuits for high-speed fiber optic data communication. Responsibilities include understanding product requirements, circuit design, schematic capture and layout in Cadence, as well as simulation and documentation.

The Principal Engineer, Digital IC Design will be responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs, including developing verification plans, test environments, and executing test cases. The role requires collaboration with various teams and delivering competitive SerDes IP solutions.

The Optical Systems Senior Staff Engineer will conduct system verification tests on coherent DSPs, compose DSP simulation models of electro-optical components, run simulations to predict module performances, and provide technical guidance to customers on platform optimization.

The Principal Analog IC Designer at Marvell will lead the design of advanced CMOS transceiver/SERDES/PLL products, focusing on circuit architecture, implementation, and performance verification using SPICE and other tools. The role includes managing a team and interfacing with various engineering teams to deliver high-quality analog IP from concept to production.

The Analog Design Engineer will analyze specifications, design and validate transistor-level analog blocks, supervise layout activities, and work with cross-functional teams to enhance existing solutions. They will also measure IC performance and debug designs to ensure simulation accuracy.

The Regional EHS Manager will support Marvell's North American operations by developing and executing EHS strategies, ensuring compliance with regulations, promoting sustainability initiatives, and providing EHS training. The role involves collaborating with various teams and reporting on EHS performance while managing external consultants and regulatory relationships.

The Senior Staff Engineer in Digital IC Design is responsible for designing, verifying, and evaluating digital circuits in high-speed data communication ICs. Key tasks include writing engineering implementation specifications, RTL design, synthesis, and timing analysis, while collaborating with various engineering teams to deliver SerDes PHY solutions.

The Senior Staff Engineer will lead ASIC physical design projects from RTL to GDS, collaborating with front-end and back-end teams to optimize floorplans, timing, and power performance. Responsibilities include debugging timing constraints, analyzing DRC/LVS results, and generating ECOs to ensure design closure. Scripting in perl/tcl and expertise with EDA tools are essential.

As a Staff Engineer for Analog Layout, you will collaborate globally to run simulations and verifications using Cadence Virtuoso, ensuring designs meet specifications. You'll be involved in the entire project lifecycle, requiring strong communication skills for status updates and presentations.

The Analog Design Engineer will design and verify mixed-signal ICs, focusing on high-speed and optical transceivers. Key responsibilities include circuit implementation (e.g., PLLs, ADCs), performance target achievement, and using standard tools for design verification. The role requires innovative problem-solving and the application of best practices in IC design.

As a Senior Staff Physical Design Engineer at Marvell, you will contribute to the physical design and methodology for high-performance processor chips. Your responsibilities include enhancing the Place and Route Flow using EDA tools, performing synthesis, timing analysis, and collaborating with the RTL design team to address design issues and optimizations.

The Principal Financial Analyst will take charge of strategic planning, budgeting, forecasting, and variance analysis. This role involves collaborating with Marketing and Engineering, developing financial models, analyzing costs and pricing strategies, and preparing financial reports for various stakeholders while ensuring compliance with financial regulations.

As a Senior Staff Analog Layout Engineer at Marvell, you will own chip/macro layouts, manage project schedules, collaborate with cross-functional teams, and contribute to team advancements through tool testing and script development, ensuring high-performance analog circuit designs meet production standards.

As a Senior Staff Application Engineer at Marvell, you will work with multi-disciplinary teams to develop hardware platforms and validate advanced semiconductor products. Responsibilities include debugging, analyzing silicon levels, developing driver firmware, and providing technical support to customers, along with creating validation test plans and scripts.

The Design Verification - Staff Engineer will develop and implement verification plans for Serdes/PHY chip designs, create and maintain testbenches, perform functional and performance verification, collaborate with design teams, analyze simulation failures, and mentor junior engineers.

The Digital Design Engineer will work within the ASIC Development team, focusing on IP/SoC architecture, designing and integrating RTL according to micro-architecture specifications, conducting code reviews, defining verification strategies, and collaborating with various teams to ensure successful delivery of projects.

As a Design Verification Engineer at Marvell, you will verify the circuitry of cutting-edge chips, working closely with design teams to create detailed test plans, develop UVM test benches, and run functional verification simulations to ensure designs meet specifications for various industries.

As a Digital IC Design Staff Engineer, you will design and verify Automotive Ethernet and Ethernet PHY front ends. Your responsibilities include writing technical specifications, designing RTL code, assisting with various closure processes, debugging design issues, and collaborating with cross-functional teams while maintaining a focus on quality.

The role involves leading product introduction phases in silicon technology, collaborating with various engineering teams to develop high-speed data center products, analyzing yield and performance, performing functional testing, and managing complex projects to ensure production efficiency.

The Principal Product Engineer will lead new product introductions focusing on silicon bring-up, collaborating with various engineering teams to ensure product reliability and performance, analyzing yield data, and managing test program issues while supporting early customer engagement.