Search the 150 jobs at Marvell Technology

As a Physical Design Engineer at Marvell, you will be hands-on with the physical design and methodology of high-performance processor chips. Responsibilities include running RTL through synthesis and PnR tools, performing Static Timing Analysis, completing DRC checks, and exploiting optimization opportunities in design processes. You'll collaborate with a global team to ensure quality and efficiency in chip design.

The Physical Design Senior Staff Engineer will be involved in developing Marvell's NSX products, focusing on physical integration, Place and Route, Power, and Physical Verification for next-generation, high-performance chips. This role requires expertise in layout implementation from floor planning to Tape-out, working closely with other engineering teams.

The Staff Engineer in Digital IC Design will focus on post-RTL design flow, including block and chip-level synthesis, timing closure, and DFT generation for high-speed SerDes IPs. This role requires collaboration with Analog/Digital design teams and support for pre and post-silicon processes, with an emphasis on improving design methodologies.

The Principal Analog IC Design Engineer will design CMOS transceiver/SERDES products, perform architectural investigations, design verification using SPICE, and supervise layout activities. The role includes lab work for design validation and collaboration with digital teams for integration and verification.

As an Analog Layout Staff Engineer, you will simulate and verify designs using Cadence Virtuoso, collaborate with designers, and participate in the project lifecycle. You will mentor and communicate updates across global teams, ensuring successful delivery of high-speed or precision analog circuits through thorough understanding and ownership of the development cycle.

As an Analog Layout Staff Engineer at Marvell, you will collaborate with global teams to run simulations and verifications using Cadence Virtuoso, ensuring designs meet specifications. You'll mentor and participate in project lifecycle meetings, providing updates and solutions on high-speed or precision analog circuits while owning the full development cycle from layout to verification.

The Staff Engineer will focus on supporting physical design and methodology for complex chip projects, including synthesis, Place and Route, and timing analysis. The role involves collaboration with global teams to enhance design processes and resolve timing issues while also developing innovative chip designs.

The Senior Engineer will work on analog design for high-speed and high-performance SerDes development in advanced technology nodes. Responsibilities include participating in SerDes architecture development, providing guidance to layout engineers, working with validation teams for IP characterization, and supporting SOC and customer IP usage and debugging.

The Staff Engineer for Physical Design will collaborate with a global team to support the physical design and methodology of complex chip projects, maintain and enhance EDA tools, perform synthesis and timing analysis, and develop solutions for timing issues.

The Senior Staff Engineer in Design Verification will be responsible for the verification of digital circuits in high-speed data communication ICs, developing verification plans, setting up test environments, and executing test cases, specifically focusing on PCIE, Ethernet, and Serdes PHY functions.

The Senior Engineer, Design Verification will focus on the verification and evaluation of digital circuits in high-speed data communication ICs. Responsibilities include verification plan development, test environment setup, modeling, and executing test-cases for innovations such as PCIE, Ethernet, and SerDes PHY using UVM methodology and System Verilog.

Responsible for designing CMOS transceivers and analog IPs for AI, Datacenter and Automotive applications. This role includes architectural investigations, circuit implementation, and collaboration with cross-functional teams. The engineer will also mentor junior staff and ensure adherence to best practices in analog design.

The role involves developing and implementing verification plans for Serdes/PHY chip designs, maintaining testbenches with verification tools, performing functional verification of digital designs, analyzing simulation failures, and mentoring junior engineers.

As a Design Engineering Junior at Marvell, you will work on developing high-speed PAM/Coherent DSPs and PHY designs. Your responsibilities include performing digital design tasks, coding in scripting languages, optimizing DSP architectures, and collaborating with cross-functional teams in a dynamic, international environment.

As a Staff Engineer, you will develop custom circuits for various technology nodes, understanding customer needs and overseeing the design process from inception to delivery. Responsibilities include designing memory and security IPs, custom analog circuits, validating hardware results, conducting failure analysis, and documenting development activities.

The Principal RTL Design Engineer at Marvell will lead a significant part of Switch design, from micro-architecture to tape-out. Responsibilities include coding micro-architected designs, integrating third-party IP, collaborating with various teams for DFT and DV, and supporting physical design for timing analysis.

The Principal Engineer will focus on verifying complex System on Chips (SoCs) and multi-SoC systems, developing verification architectures, writing test plans, developing tests, debugging failures, and maintaining verification tools for multicore SoCs.

The Principal Analog Mixed-Signal Design Engineer will be responsible for the design and validation of RF and analog circuits for high-speed broadband ICs, focusing on Transimpedance Amplifiers and optical interface chips. The role involves active circuit design, technical leadership, and collaboration on post-silicon validation and transition to mass production.

Design and implement advanced CMOS transceiver/SERDES products, focusing on architectural investigations and verification for various analog circuits. Responsibilities include layout activities, lab testing, and support for design integration with digital teams.

The Principal Digital Design Engineer will assist in chip design and verification for optical Ethernet transceiver ASICs, focusing on high-speed data path RTL implementation, ASIC specification, and team mentorship. Responsibilities include managing entire design cycles, post-silicon debug, and collaborating with backend teams to ensure product functionality.