Senior Principal Engineer, Verification (Ethernet, Serdes, UVM)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell Semiconductor is seeking a highly skilled and experienced Senior Principal Verification Engineer to join our dynamic team in Santa Clara, CA. The ideal candidate will have extensive experience in verification methodologies with a strong emphasis on Ethernet, SERDES, and UVM. As a Senior Principal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our cutting-edge semiconductor products.

What You Can Expect

• Develop and execute comprehensive verification plans for complex semiconductor designs, with a focus on High-Speed Serdes PHY/Ethernet functionality.
• Architect and implement advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Design and develop reusable verification components and test benches to accelerate verification closure.
• Collaborate closely with cross-functional teams including design, architecture, and software teams to ensure seamless integration of verification strategies.
• Analyze and debug test failures to identify root causes and drive resolution.
• Lead and mentor junior team members and provide technical guidance to enhance team expertise.
• Develop and execute comprehensive verification plans for complex semiconductor designs, with a focus on High-Speed Serdes PHY/Ethernet functionality.
• Architect and implement advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Design and develop reusable verification components and test benches to accelerate verification closure.
• Collaborate closely with cross-functional teams including design, architecture, and software teams to ensure seamless integration of verification strategies.
• Analyze and debug test failures to identify root causes and drive resolution.
• Lead and mentor junior team members and provide technical guidance to enhance team expertise.

What We're Looking For

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of industry experience in IP/SOC/ASIC verification with 3+ years of leading DV teams
• Strong verification expertise and hands-on experience with SystemVerilog and UVM
• Proficiency in various verification methodologies and demonstrable experience with industry-standard tools for verification, simulation, and emulation
• Extensive experience in verifying PCIE/Ethernet PHY protocols (e.g., Ethernet MAC, Ethernet Switch) and VIP is a plus.
• Experience with scripting languages such as Perl, Python.
• Solid understanding of digital design concepts and ASIC/FPGA design flow.
• Experience with DV test plan and coverage-driven constraint randomization testing
• Excellent cross-discipline communication and interpersonal skills
• Strong problem-solving abilities with keen attention to detail.
• Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Hands-on experience with PHY/SERDES verification is advantageous.
• Previous experience in mentoring or leading verification teams.
• Knowledge of High Speed PHYs, Ethernet PHY, MAC, Interoperability, Clauses CL72/92/136/162/178, Serdes 112G/224G per lane
• Working with vendor Ethernet VIP’s and test suites
• MATLAB and C/C++ based system simulation and evaluation, Systems C, DPI-C

Expected Base Pay Range (USD)

168,920 - 253,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

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