Senior ASIC Implementation Engineer

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How You Will Contribute:

This role is to contribute as part of the ASIC integration team to the front-end design activities for Ciena’s Modem ASICs prior to the release to layout. The individual will be responsible for executing implementation activities such as synthesis and static timing analysis for various subsystems as part of the ASIC development process.

An ASIC implementation engineer is mainly responsible for front end ASIC design activities prior to the design being handed off to the back-end implementation team. These activities will involve working to integrate various subsystems into the overall ASIC and working with the internal IP teams to ensure that physical implementation requirements are met.

The successful candidate will be involved in and responsible for several of the following activities:

•  Working as part of the ASIC integration team performing front-end implementation activities including, but not limited to, synthesis, static timing analysis, logical equivalence checking, and clock domain crossing checking prior to the design being handed off to the physical implementation team for layout.
• Working with various internal IP teams to understand the subsystem requirements as it pertains to physical implementation and ensuring the IP team is developing an implementable design.
• Ownership for the synthesis and front-end design activities of various IP subsystems and their delivery into the ASIC following the project schedule.
• Developing and maintaining static timing constraints for synthesis and timing signoff for those assigned IP subsystems
• Running logical equivalence checking for those sub-systems to prove equivalence between RTL and various representations of gate level netlists (pre and post layout)
• Validating clock domain crossings within the top level of the ASIC
• Working with the layout team(s), both internally and externally, to ensure alignment of the synthesis process to back-end activities.
• Contributing to the evolution of the synthesis and STA methodology as used in deep-submicron processes.
• Working regularly with external tool vendors to ensure tools flows are compliant and successful.
• Developing scripts and tools to aid in the implementation of the synthesis and STA processes
• Implementation of ECO’s as required

Depending on the phase of required projects, time will be spent both on implementation methodology improvements and infrastructure and the delivery of IP subsystems into various ASICs.

The Must Haves:

• Bachelors Degree or equivalent
• Minimum of 3 years of experience using synthesis and/or STA tools as part of the ASIC process
• Wide range of knowledge in ASIC implementation including synthesis, static timing analysis, logical equivalence checking and clock domain crossing validation using various tools and targeting multiple technologies
• Able to work with various design teams as well as the integration and backend teams – good interpersonal skills are expected
• Ability to work independently with little supervision and take ownership for assigned responsibilities and associated schedules

Assets:

• Experience in RTL design
• Experience with other design activities including floorplanning, DFT and P&R

Pay Range

The annual pay range for this position is $100,900 - $161,100

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