At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Principal Verification Engineer (Memory)
Location: Cork
Reports to: Design Engineering Director
Job Overview:
The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume.
This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry.
The Principal Verification Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India.
Job Responsibilities:
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Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage.
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Development of UVM-SV Scoreboards for self-checking regressions.
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Development of Functional Coverage as part of Metric Driven Verification Environments.
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Development of SystemVerilog Assertions for use in Formal and Simulation Environments.
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Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
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Creation and Management of Automated Regression Environments, e.g. Jenkins.
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Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
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Close Collaboration with Design Engineers to debug complex test scenarios.
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Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.
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Work across disciplines with Design, Support, Delivery, Application Engineers, PHY team, etc.
Job Qualifications:
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Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
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10-15 years’ experience in microelectronics/EDA industry.
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Experience of SystemVerilog Constrained Random Verification essential.
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Experience of Metric Driven Verification (MDV) essential.
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Excellent oral and written English essential.
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Self-motivated with excellent planning, interpersonal, and communication skills.
Additional Skills/Preferences:
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Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred.
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Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
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AXI and/or CHI-E experience is highly desirable.
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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