Principal Product Engineer

Posted 14 Days Ago
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Cary, NC
154K-286K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The Principal System Engineer will engage with customers to review SerDes IP integration, resolve integration issues, conduct design reviews, support silicon debug, and provide feedback for product improvement. They will generate technical specifications and contribute to R&D for high-speed SerDes IP products.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Product Engineer
 

This is a unique opportunity to join the rapidly growing Product Engineering team at Cadence Design Systems. We are looking for a Principal Product Engineer who will be the main technical interface on Key Customer engagements deploying our advanced DDR PHY IP and SERDES IP.  This is a hands-on technical position and candidate must have experience in deploying and supporting IP in Post Silicon Phase.

Responsibilities:

  • Main technical interface between R&D team and tier one customer teams handling resolution of technical issues predominantly in post silicon realm.
  • Primary technical contact for customer SOC and system integration questions.
  • Engage with IP customers to review Serdes/DDR IP integration guidelines, provide integration training and recommendations to customer
  • Collaborate with Analog/Digital design, DV teams and Program Management to support customers with ATE deployment, silicon bringup and production ramp.
  • Actively participate in Cadence silicon evaluations and demos.
  • Be voice of the customer and lead initiatives within the team for improvement of collateral to enhance customer experience with the IP.
  • Co-ordinate and lead onsite bringup for tier 1 customers.

Position Requirements:               

  • M.S. Electrical/Computer Engineering (or similar degree) and 5 + years of experience or PhD and 1+ Years of relevant experience
  • Experience working with Memory PHY, Memory Controller and DRAM
  • Experience with high-speed Serdes and serial link architecture, circuit blocks, and performance matrix
  • Experience using advanced mixed signal verification, and system simulation tools.
  • Strong debug and problem-solving skills.
  • Strong background in supporting Post Silicon bringup and debug.
  • Must have strong presentation and communication skills.
  • Experience with lab equipment to reproduce customer failures in the lab.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Top Skills

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The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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