Principal Engineer, RF PLL Design

Principal Engineer, RF PLL Design:

 In this role, you will be partnering with a team of cross functional engineers to develop novel SoC products for connectivity and communications. This position has high visibility and impact on the success of the project and may also oversee a team of RFIC design engineers.

InnoPhase IoT offers several office locations in CA and a hybrid remote/office work environment providing an excellent balanced workplace for a results-oriented individual committed to continuous improvement, learning, and collaboration. This position can be based either in San Diego (preferred) or in San Jose.

Key Responsibilities:

• Technical leadership in developing custom RF, analog, and mixed signal IPs.
• Hands on contribution on all aspects of the design of high-performance RF frequency synthesizers in advanced CMOS processes.
• Supervising layout activities and performing post-layout LPE simulations and analysis.
• Working closely with RF, analog, digital, test, and firmware design engineers.
• Presenting to peers and management.
• Working with the System Engineers to derive block level specifications based on target product requirements.
• Run behavioral model simulations to study system performance and drive block-level specifications (Matlab, VerilogA).
• Partnering with the System and Digital Engineers to design and validate methods and algorithms to alleviate circuit impairments by calibration, compensation, pre-distortion, and various other techniques.
• Assisting Test Engineers on the design of comprehensive test plan, including defining, developing, and ramping up production ATE solutions.
• Participating in post-silicon bring-up, detailed performance characterization, optimization, and debug including the use of lab instruments.

Job Requirements:

• MSEE minimum, PhD preferred.
• 12+ years of hands-on experience in high-performance RF, Analog and Mixed Signal IC design in advanced CMOS processes.
• Excellent technical knowledge of RF CMOS fundamentals and transistor level design and implementation of sigma-delta fractional-N RF PLLs.
• Good understanding of loop design optimization for PN/jitter, spurs, locking time, area, etc.
• Hands on experience in transistor-level design of the RF Frequency Synthesizer related circuits, such as: RF VCO, PFD, Charge-Pump, Loop-Filter, MMD, Dividers, LO routing, XO, frequency multipliers, etc.
• Familiarity with RF device modeling, including inductor EM simulation, packaging effects, ESD structures, and supply isolation.
• Good familiarity with IC layout, full IC design flow and verification.
• Strong intuitive, analytical, and problem-solving skills, strong initiative, attention-to-detail, highly organized, and personal commitment to quality.
• Proficiency in using various development tools: Cadence Virtuoso suite, EMX, Calibre, PVS, Matlab, MS Office, etc.
• Team player with a strong sense of urgency to meet product timeline.
• Ability to work well on multiple tasks simultaneously.
• Ability to work well on multi-site teams.
• Excellent written and verbal communication and presentation skills, including the ability to articulate and explain circuit and system design decisions for both internal design documents and external reports or proposals.

Desirable Skills:

• Direct experience in IoT, WiFi and Bluetooth products, circuits, and systems.
• Direct experience in wide tuning range RF VCO and RF PLL designs.