The Embedded Software Engineer will design, develop, implement, and test RF drivers for InnoPhase IoT’s SoC products, collaborate with RF and systems teams to document software procedures, and troubleshoot existing code. Hands-on testing with lab equipment is also required.

The Senior Staff DFT Engineer will architect and support DFT for new IoT products, utilizing DFT/ATPG/MBIST tools, assisting in bringup and ensuring quality in manufacturing tests, and integrating DFT within constraints. Responsibilities also include debugging and supporting design teams.

The Staff Software Engineer will design and implement security features for IoT solutions, analyze and test vulnerabilities in firmware, support customer trials, and manage security certifications. The role requires strong experience in embedded software and secure software development lifecycle.

The Principal Engineer will lead the design and development of analog and mixed-signal ICs, particularly ADCs in CMOS processes. Responsibilities include technical leadership, supervising layout activities, conducting behavioral model simulations, and collaborating with cross-functional teams for product development and testing.

Design and develop firmware for wireless IoT solutions, lead the development of 802.11 MAC firmware, and collaborate with international teams to deliver end-to-end ecosystem solutions.

The Staff/Sr. Staff PHY Design Engineer at Innophase IoT is responsible for developing micro-architectures and RTL for low-power wireless communication protocols. This role involves designing digital signal processing engines, analyzing design bottlenecks, and collaborating with verification teams on testing plans and physical design elements.

You will implement MAC and PHY algorithms for low power IoT connectivity devices, develop specifications from standards, create micro-architectures using Verilog/SystemVerilog, and collaborate with RF/baseband and firmware teams. Special focus will be on low power design aspects and working with ASIC/FPGA implementation teams.

In this role, you will lead and contribute to the design of high-performance custom RF, analog, and mixed signal IPs. Responsibilities include supervising layout activities, collaborating with cross-functional teams, presenting work, and engaging in post-silicon performance characterization and optimization.

As a PHY Design Engineer/Lead at InnoPhase IoT, you will develop low-power WiFi and Bluetooth micro-architecture, participate in RTL design, analyze designs for bottlenecks, develop verification tools, and work with physical design teams. You’ll utilize your extensive experience in ASIC and FPGA development to drive innovations in wireless IoT solutions.

The PHY Verification Engineer/Lead will handle Low-power WiFi and BT/BLE verification, design development, UVM testbench design, test planning, and collaborate with systems and design engineers to optimize verification processes and coverage.

The Principal Engineer, RFIC Design will lead and contribute to the design of custom RF, analog, and mixed signal IPs while supervising layout activities and collaborating with various engineering teams. Responsibilities include running simulations, developing test plans, and participating in post-silicon debugging and characterization.

The Python Build Automation Developer/DevOps Engineer will be responsible for build automation using Python scripts, Gitlab CI/CD setup, and integrating various tools for efficient software development. They will support teams in Git operations and manage JIRA Service for workflow customization.

The Principal Engineer will lead a team to develop custom analog and mixed-signal IPs for SoC products, focusing on power management and biasing circuits, while collaborating with cross-functional teams for integrated product requirements and design validation.

The Principal Engineer, Physical Design at InnoPhase IoT is responsible for the complete SOC implementation and verification flow from RTL to GDS. Responsibilities include synthesis, floorplanning, place and route, timing verification, and collaborating with the SOC design team to ensure design feasibility and performance. Strong experience in low-power design and chip integration is required.