Cadence Design Systems

Lead Design Engineer

Posted 19 Hours Ago

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Pune, Maharashtra

Mid level

Cloud • Hardware • Software • Semiconductor

The Role

The Lead Design Engineer at Cadence is responsible for ASIC design and verification, particularly in the PCIe and storage domains. The role requires strong debugging skills and effective communication to tackle complex technological challenges.

Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.

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The Company

HQ: San Jose, CA

8,216 Employees

On-site Workplace

Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.