Graduate Intern Technical - ATPG

Job Details:

Job Description: In this position you will be involving in the training design and development of next generation Server SOCsCPUs Your responsibilities will include some of the following but not limited to Assist design unit owner in Register Transfer Level RTL modeling amp functional validation Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next generation deep submicron embedded circuit solutions Verify the circuit behavior against the original simulation model and first silicon Define VLSI Structural Design methodology and developing design flows Implement structural physical designs such as synthesis floor planning powergrid and clock tree designs timing budgeting and closure place and route RCextraction and integration Verify structural physical designs such as functional equivalency timingperformance noise layout design rules reliability and power

Qualifications:You should be a student Post graduateMasters MEMTechMS currently pursuing studies in relevant field with good understanding of semiconductor physics and basic PC computer architecture Additional qualifications include Familiarity with Very Large Scale Integration VLSI Complementary MetalOxide Semiconductor CMOS logic circuit design Well versed in UNIX C programming and relevant Computer Aided Design CAD tools

Job Type:Student / Intern

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Legal Disclaimer:

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.