Design Verification, Senior Staff Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution.

As a senior member in the team, he/she will focus on improving the design verification methodology and flow. Work cross-function with analog and DSP teams to achieve high-quality analog mixed-signal verification.

The responsibilities include but not limited to.

• Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Use and improve UVM DV environment
• Improve the design methodology and flow.
• Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon

What We're Looking For

MSEE with 8+ years of experience.
 

Good personal communication skills and team working spirit.

Hardworking and motivated to be part of a highly competent design team.

Good communication and leadership skills to work with a global team.

Must be proficient in the following skills:

• Fundamental concepts in digital logic design
• Understand ASIC verification flows and methodologies
• Verilog, SystemVerilog, UVM
• UNIX Shell scripting (Csh, Bash)

Highly desirable skills:

• Experience with VIPs
• Formal verification
• Low power design
• MATLAB and C/C++ based system simulation and evaluation
• DSP function hardware implementation knowledge
• Strong Perl and Python scripting

Expected Base Pay Range (USD)

121,840 - 182,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

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