Silicon Design verification for High performance Coherent Fabric following
coherence protocol like MESI etc., collaborate closely with architect team, RTL designer
team, and other Fabric verification teams to define functional correctness. Develop tests
using assembly, C/C++, SystemVerilog, or test vectors based on predefined plans, while
also creating coverage monitors to assess comprehensive feature coverage and reach
tape out quality. Implement SystemVerilog or C-based checkers for design end-to-end
verification, write assertions, and employ formal verification techniques to assess design
correctness if needed. Develop test bench from scratch and create of
directed/constrained random test cases. Diligently investigate and triage test failures
from RTL simulations, and meticulously track and document identified issues. Manage
project schedules, offer support for cross-functional engineering efforts, and assist in
enhancing verification workflows, automation scripts, and regression testing procedures.
Education:
- Master’s or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
Experience:
- None
Special Requirements: Must have prior coursework or project experience in each of the following::
- Cache coherence protocol and network-on-chip design.
- Debug and triage simulation test failures via waveform and logs.
- Object oriented programming, C, C++, System Verilog, Python, Perl, and algorithm.
- Parallel Computer Architecture.
- **Telecommuting allowed for this position**
Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054
Applicant Instructions: Email resume to: j[email protected]. Include job code 91887 in reply. EOE.
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What We Do
Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise
