Search the 29 jobs at Rivos

The DL Communications Collectives SW Engineer will design and implement optimized communication libraries for distributed systems used in deep learning. Responsibilities include working with GPUs, optimizing low-latency communication, collaborating with hardware teams, and validating library performance. The role demands strong problem-solving skills and a collaborative mindset in a fast-paced environment.

As a Senior Power-Management Architect, you will model and optimize power-performance features, collaborating with various teams to define power management features, prototype them, and assist in the characterization of the power management architecture in Rivos’ devices.

As a Silicon Emulation Engineer, you will develop and debug emulation and FPGA-based prototyping systems for SOC projects. Responsibilities include creating emulation models from RTL, driving SOC bring-up, and improving methodologies for emulation efficiency.

The AMS DV engineer will lead design verification for droop sensing, clocking, PLL, LDO, On-die VRs, and PMICs using cutting-edge finfet technology. Responsibilities include creating UVM benches, developing verification plans, writing assertions, and integrating analog design IPs for simulation and emulation.

As a Logic Equivalence Check Engineer, you will develop and enhance verification flows, support design teams, and collaborate with tool vendors to debug issues. Your role involves maintaining CAD tools and implementing efficient low power flows while working with RTL, PD, and DFT teams.

The Logic Equivalence Check Engineer will develop and improve logical equivalence check flows, debug processes, and collaborate with design teams and tool vendors. Responsibilities include building automation for formal verification, creating custom solutions, and maintaining in-house CAD tools.

As a Senior/Principal Deep Learning and Large Language Model Performance Architect, you will analyze workloads, model performance, validate results pre- and post-silicon, and propose improvements for enhancing software performance while collaborating with cross-functional teams in the evolving AI landscape.

The job involves developing advanced test generation strategies to validate accelerator designs, collaborating with hardware and software engineers, and profiling and tuning test generation code. The role emphasizes creativity in designing test vectors and understanding instruction set architectures (ISA) for effective debugging.

The Senior Memory Design Engineer will lead the development of custom SRAM and register file memories to enhance circuit performance and power optimization. This role emphasizes on design from scratch, circuit simulation, power characterization, and collaboration with various teams for successful product delivery.

The FPGA Design Engineer will be responsible for developing and verifying FPGA designs, bringing hardware to life through lab testing and debugging, and potentially expanding into firmware development. The role requires working collaboratively on complex projects and applying theoretical knowledge to practical applications.

The Memory Controller Verification Engineer will verify digital verification aspects such as functional performance and DFT of DDR and HBM memory subsystems. Responsibilities include working with design teams, developing testplans and testbenches, debugging, and providing support for emulation and silicon bring-up processes.

As a Silicon Physical Design Verification Manager, you will develop PDV methodologies, manage a team of engineers, perform full chip integration, ensure the quality of deliverables, and work cross-functionally to meet project milestones in a fast-paced environment.

This role involves designing and developing SRAM and custom memory circuits to optimize performance and power efficiency. Responsibilities include collaborating with various teams, performing design simulations, and ensuring high-quality deliverables in a fast-paced environment.

The Senior Memory Design Engineer role involves developing custom SRAM and register file memories to enhance circuit performance while optimizing power usage. The candidate will manage the complete design process, conduct sizing estimates, and collaborate with various teams to ensure high-quality designs. Post-silicon testing and problem-solving are also key responsibilities.

The Senior Memory Design Engineer will lead the design and development of high performance SRAM and register file memories. Responsibilities include conducting PPA analysis, collaborating with microarchitecture and physical design teams, delivering design collateral, and performing post-silicon testing and debugging.

The DFT Engineer will design and validate DFT features, create test structures and plans, and oversee the testing processes. Responsibilities include collaborating with the design team, ensuring DFT requirements are met, and running tests as needed.

The Senior Memory Design Engineer will develop advanced custom memories, optimize power performance, and support silicon bring-up. Responsibilities include designing SRAM and related circuits, conducting PPA analysis, ensuring design quality, and collaborating closely with various teams for successful product implementation.

As a Post-Silicon Power Engineer, you will analyze workloads for power dissipation, conduct silicon power validation, and collaborate with various teams to enhance power performance ratios. Your role includes automating measurements and debugging system-level performance issues.

The Senior Memory Design Engineer will lead the design and development of high-performance SRAM and custom circuits, focusing on low power optimization and circuit performance metrics. Involved in PPA analysis, collaboration with microarchitecture and physical design teams, and leveraging advanced FinFET technology. The role requires strong problem-solving skills to deliver quality designs under tight deadlines.

The DFT Engineer will focus on designing DFT features, define test structures, create test vectors, collaborate with teams to ensure requirements are met, validate DFT requirements, and verify designs through testing. The role emphasizes teamwork and productivity under tight schedules.