The Senior Power-Management Architect will model and optimize power/performance features for Risc-V based accelerated computing platforms. Responsibilities include analyzing workloads, defining power management features, collaborating with design teams, and assisting with post-silicon bringup.

The Senior Power-Management Architect will model and optimize power/performance features for Risc-V based accelerated computing platforms. Responsibilities include analyzing power behavior, defining power management features, collaborating with teams to bring new features to production, and assisting with post-silicon characterization.

As a Senior Power-Management Architect, you will model and optimize power/performance features on Risc-V based computing platforms, collaborating with various teams to enhance power management architecture and ensure product-level quality and efficiency.

The Senior Power-Management Architect will model and optimize power/performance features on Risc-V based computing platforms. Responsibilities include collaborating with various teams to enhance power management features, analyzing workloads, and assisting in post-silicon characterization of power-management architecture.

As a Logic Equivalence Check Engineer, you will develop and improve verification flows, automate processes, and collaborate with design teams. Responsibilities include building logical equivalence checks, debugging with various tools, and developing in-house CAD tools while working closely with tool vendors and cross-functional teams.

The AI Software Engineer will develop components for an AI software stack, port AI applications to new hardware platforms, tune AI applications, implement mathematical operators, and validate AI models. The role requires strong problem-solving abilities and collaboration skills.

As an Analog Engineer, you will lead the design of advanced mixed-signal circuits, writing specifications and collaborating with architecture and verification engineers. Responsibilities include behavioral modeling and supporting integration and characterization efforts. You will ensure high-quality silicon through effective communication with team members and external vendors.

As a Senior Power-Management Architect, you will model and optimize power-performance features, collaborating with various teams to define power management features, prototype them, and assist in the characterization of the power management architecture in Rivos’ devices.

As a Memory Controller Verification Engineer, you will verify the functional and performance aspects of DDR and HBM memory subsystems, develop test plans, and integrate various verification components. Responsibilities include debugging and providing support to emulation teams as well as collaboration with global teams.

As a memory subsystem design verification engineer, you will verify DDR and HBM memory subsystem designs, collaborating closely with architects and design teams. Responsibilities include developing test plans and testbenches, integrating VIPs, creating test stimuli, debugging, and providing support for emulation and silicon bring-up teams.

The Analog Mixed Signal Design engineer will lead the design of analog circuits like LDOs, PLLs, and more for advanced silicon projects. Responsibilities include writing specifications, collaborating with engineers, modeling circuits, and managing IP development and verification.

As a Silicon Emulation Engineer, you will develop and debug emulation and FPGA-based prototyping systems for SOC projects. Responsibilities include creating emulation models from RTL, driving SOC bring-up, and improving methodologies for emulation efficiency.

The Silicon Product eFA Engineer will conduct fault isolation for new product development and customer returns, employing various testing techniques to identify root causes of manufacturing defects. This role collaborates with design teams and may involve travel, with a focus on improving silicon quality and performance based on analysis.

The Silicon ATE Product Engineer will lead the productization of semiconductor chips, create test plans for SoC characterization, analyze test data and implement voltage guard-bands. The role includes collaboration with cross-functional teams to ensure quality product delivery and conducting correlation analysis for design improvements.

The AMS DV engineer will lead design verification for droop sensing, clocking, PLL, LDO, On-die VRs, and PMICs using cutting-edge finfet technology. Responsibilities include creating UVM benches, developing verification plans, writing assertions, and integrating analog design IPs for simulation and emulation.

The Logic Equivalence Check Engineer will develop and improve logical equivalence check flows, debug processes, and collaborate with design teams and tool vendors. Responsibilities include building automation for formal verification, creating custom solutions, and maintaining in-house CAD tools.

As a Logic Equivalence Check Engineer, you will develop and enhance verification flows, support design teams, and collaborate with tool vendors to debug issues. Your role involves maintaining CAD tools and implementing efficient low power flows while working with RTL, PD, and DFT teams.

As a Senior/Principal Deep Learning and Large Language Model Performance Architect, you will analyze workloads, model performance, validate results pre- and post-silicon, and propose improvements for enhancing software performance while collaborating with cross-functional teams in the evolving AI landscape.

The job involves developing advanced test generation strategies to validate accelerator designs, collaborating with hardware and software engineers, and profiling and tuning test generation code. The role emphasizes creativity in designing test vectors and understanding instruction set architectures (ISA) for effective debugging.

The Senior Memory Design Engineer will lead the development of custom SRAM and register file memories to enhance circuit performance and power optimization. This role emphasizes on design from scratch, circuit simulation, power characterization, and collaboration with various teams for successful product delivery.