Search the 29 jobs at Rivos

The role involves silicon design verification, developing tests to ensure functional correctness using assembly, C/C++, and SystemVerilog. Responsibilities include writing assertions, creating a test bench, investigating test failures, and enhancing verification workflows. The position requires collaboration with various engineering teams.

The Multi-Chiplet Fabric Performance Engineer will define multi-chiplet interconnection solutions, create performance models for bandwidth estimation, and debug performance issues. This role involves collaborative work on architecture and implementation, ensuring the performance of RTL designs aligns with targets, while also developing tests for model quality.

As an FPGA Design Engineer, you will design and implement FPGA RTL, build verification environments, and debug FPGAs and systems. This role offers the chance to expand into firmware development and requires teamwork and problem-solving skills.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

As a Memory Controller Verification Engineer, you'll verify the digital logic aspects of DDR and HBM memory subsystems, develop test plans and testbenches, integrate verification IPs, and collaborate with design teams and third-party vendors. You'll also engage in debugging and regression activities, ensuring robust memory interface performance.

The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.

The Senior Memory Design Engineer will develop custom SRAM and register file memories to enhance circuit performance while optimizing power. Responsibilities include designing custom circuits, conducting PPA analysis, collaborating with various teams for design implementation, and ensuring high-quality design collateral. A solid background in circuit design and low power techniques is essential.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories. Responsibilities include driving the design and development of custom cells for high performance and low power designs, conducting PPA analysis, equivalence checking, collaborating with various teams, and delivering high-quality design collateral.

The Fabric/Interconnect Architect will design and specify internal interconnect architectures for computing platforms, focusing on both coherent and non-coherent interconnects. They will collaborate with the silicon team on performance, power, and area specifications, ensuring high-level architectural goals are met through detailed design and validation plans.

As a Post-Silicon Power Engineer, you will analyze workloads and their power dissipation, measure silicon power dissipation, improve power/performance ratios, and collaborate with cross-functional teams. Responsibilities include conducting power measurements and debugging system-level performance.

As Fabric/Interconnect Architect, you will develop and specify internal interconnect architecture, covering both coherent and non-coherent systems. You will collaborate with the Silicon team to ensure power, performance, and area requirements are met while reviewing validation plans for functionality and performance.

The Senior Memory Design Engineer will develop custom SRAM and register file memories while optimizing performance and power. Responsibilities include circuit design from scratch, working with the microarchitecture team, conducting sizing estimates, collaborating with various teams, and ensuring quality in design collateral.

The DFT Engineer role involves defining strategies for DFT design, creating test structures, and collaborating with various teams to ensure compliance with DFT requirements. Responsibilities also include validating designs, designing DFT features, and debugging.

As a Memory Subsystem Architect, you will specify memory subsystem architecture, working closely with software and silicon teams to define performance, power, and area requirements. Your role involves collaborating with industry groups and memory vendors, contributing to micro-architecture specifications, and conducting technical investigations for validation.

Lead the design verification for Analog Mixed-Signal (AMS) designs, focusing on droop sensing, clocking, PLL, LDO, On-die VRs, and PMICs. Responsibilities include creating UVM testbenches, writing assertions for properties, analyzing coverage, and integrating analogue design IPs for simulation and emulation.

Lead the design of analog blocks for advanced mixed-signal circuits in a startup focused on high performance computing. Responsibilities include developing specifications, collaborating with engineers, and ensuring design verification. Additionally, manage integration efforts and work with external vendors on characterization.