Design Engineering Architect

Posted 15 Hours Ago
Be an Early Applicant
San Jose, CA
169K-315K Annually
Expert/Leader
Cloud • Hardware • Software • Semiconductor
The Role
The Design Engineering Architect will lead the development of physical aware IP architectures, collaborating with foundries and guiding design teams on best practices, ensuring high Performance/Power/Area. This role demands extensive experience in design tools and cross-functional project management in semiconductor IP development.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Architect

The Cadence Silicon Solution Group (SSG) develops industry leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud and AI for SoC and chiplets. At Cadence we are helping set the standard on IP products that get integrated in SoCs and chiplets powering the world’s Data Centers, Automobiles, Cloud, wired/Wireless, and AI enabled systems. Cadence SSG IP business is growing fast. We are expanding our San Jose team and looking for smart, energetic, collaborative, and creative people to join this exciting growth opportunity and help us lead the industry with Cadence IP products for silicon solutions. Do you want to make a difference and be challenged?

Design Engineering Architect in physical design, SSG.

• This technical and project leadership role is responsible for working with IP design teams and silicon solution architects to develop new physical aware IP architectures, collaborating with leading foundries such as TSMC, Samsung, Intel to achieve best Performance/Power/Area (PPA) for Cadence IPs, and guiding Cadence worldwide physical design teams to follow the best design practices and methodologies.
• The position requires 15+ years of experience in design tools, foundry technologies and proven leadership in collaborating and coordinating cross functional teams and external companies to develop industry-leading IPs for advanced technology nodes at world leading semiconductor foundries. 
• Cross functional project management experience with strong communication and inter-personal skills are required.
• Thorough understanding and experience with the full physical design flows including RTL Synthesis, floorplan, P&R, high performance clock-tree synthesis, static Timing analysis and closure, DFT, Low power design techniques, Physical verification.
• Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus, Cerebrus).

The annual salary range for California is $169,400 to $314,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

P&R
Rtl Synthesis
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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