Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Digital Design Engineer’s primary responsibility will be the RTL design. This will include function definition, micro architectural specification, design, simulation, verification and synthesis.

Job Responsibilities:
• Contribute to design, architecture and specifications of the IP blocks
• Verify and debug IP blocks
Job Qualifications:
• BS or MS in Electrical Engineering or Computer Science
• RTL design experience desired with Verilog/System Verilog
• Strong debugging and analytical skills
• Digital architecture trade-offs for power, performance and area
• Handling of multiple asynchronous clock domains and their crossings (CDC)
• RTL lint checks and proper resolution of errors
• Working knowledge of UNIX/Linux, shells, programming and scripting
• Effective communication skills and ability to work remotely
• Team player (fluent in English)
• At least 2 years of applicable experience
• Must be legally eligible to work in Poland

Additional Skills/Preferences:
• Exposure to modern digital verification flows: functional coverage closure, metric-driven verification, formal verification, etc.
• Knowledge of processor-based systems and embedded programming
• Semiconductor IP design / FPGA design experience is beneficial
• Working knowledge of leading protocols (i.e. PCIe, CXL, AMBA, Ethernet, USB, …)
• Ability to use UVM TB

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