Design Engineer

Posted 8 Days Ago
Be an Early Applicant
San Jose, CA
132K-244K Annually
Junior
Cloud • Hardware • Software • Semiconductor
The Role
The Design Engineer position at Cadence involves working on the next generation emulation processors as part of the Palladium ASIC development team. Responsibilities include RTL development of complex ASIC/SoC, using Verilog and SystemVerilog, understanding ASIC design flow, and working with design tools like Incisive, NCSim, Genus, Design Compiler, STA, power analysis, Lint, and CDC. Exposure to major IP and protocols like SERDES, PCIe, and DDR4 is also required. The position offers annual salary range of $131,600 to $244,400 with additional incentive compensation and benefits.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the Palladium emulation platform which is an industry leading emulation platform used for emulating complex custom silicon designs used by top semiconductor industries globally . The Palladium platform is a scalable emulation platform that can emulate multi-Billion gate designs with very high amount of memory while maintaining the scalability of the usage modes and debug tools.

The Palladium ASIC team has a wide range of expertise from building large multi-chip devices to integrating such high power devices into complex scalable enterprise grade hardware. The design / verification / physical design of these ASICs pushes various tools to their limits.

This particular position requires the individual to be part of ASIC Design effort of the next generation emulation processors

Job Requirements:

  • Bachelor’s in Computer Science or Electrical Engineering + 2 years of related experience; or Master’s
  • Experience in RTL development of complex ASIC/SoC.
  • Comfortable in Verilog and SystemVerilog for the development of complex logic systems.
  • Aware of ASIC design flow. Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis.
  • Experience with Lint and CDC tool flows.
  • Exposure to some major IP and protocols, such as SERDES, PCIe and DDR4.
  • Self-driven. Good communication, organization, analytical, presentation and people skills.

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Systemverilog
Verilog
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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