Design Automation Engineer for MPS Engineering

Job Details:

Job Description: 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below.

Life at Intel

Diversity at Intel

Intel's Multi-Product Shuttle (MPS) Software Engineering team is looking for an EDA/CAD tools Software Design Automation Engineers.

The Design Automation engineer for MPS will support various aspects of VLSI design automation tasks includes but not be limited to:

• Defining and implementing verification scripts/flows to ensure TestChip designs meet tapeout requirements.
• Developing computer aided design (CAD) automation flows for physical design verification, Design Rule Checking (DRC), layout synthesis and validation.
• Performing audits of VLSI layout to help ensure layout convergence for tapeout schedule readiness and design database acceptance for tapeout.
• Providing customer support to TestChip passengers during design tapeout executions (includes design rules, fullchip layout collaterals, tapeout requirements/procedure).

Successful candidates should exhibit the following behavioral traits:

• Communication skills with the ability to convey technical contents.
• Attention to details and tolerance to ambiguity.
• Highly motivated individual with a 'can-do' attitude, willingness to take informed risks in order to achieve desired team goals.
• Strong communication skills with the ability to clearly/concisely convey technical content, teamwork, and ability to meet the deliverables schedules.
• Attention to details and discipline in implementing defined methodologies.
• High tolerance to ambiguity, ability to efficiently define concrete architecture and design strategy/plans.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

• US Citizenship required.
• Ability to obtain and maintain an active US Government clearance (TS/SCI.
• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering and/or similar engineering degree. Relevant experience in lieu of degree will also be considered. 
• 3+ years of experience in the following:
  • Exposure with industry standard integrated circuits (IC) design CAD tools/flows such as Siemens Calibre, Cadence Virtuoso, or Synopsys IC WorkBench.
  • Experience with software development/programming in high-level languages (e.g. Perl/Python/ Shell/TCL/C++) and IC CAD tool scripting languages (e.g. Siemens Calibre or Synopsys ICValidator).
  • Experience in VLSI circuit, CMOS layout design and validation.

How to Stand Out (Preferred Qualifications):

• Candidates 10 + years of experience are encouraged to apply
• Active US Government Security Clearance, with a minimum of Secret.
• Experience working on with UNIX/Linux computer platforms.
• Demonstrated capacity to solve complex problems using efficient computer algorithm and effective programming techniques.
• Demonstrated expert level understanding of layout design rules and familiar with runset or rule-deck coding development.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

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Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$146,520.00-$206,860.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.