Custom VLSI Layout and Automation Engineer

Posted 22 Hours Ago
Be an Early Applicant
2 Locations
Senior level
Semiconductor • Manufacturing
The Role
This role involves laying out custom circuit blocks in advanced nodes, performing block-level DRC and LVS, creating custom block views, and automating layout and GDS manipulation tasks. The engineer must be proficient in Python and TCL scripting, with experience in advanced-node layout design and backend EDA tools.
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Job Description

Custom VLSI Layout and Automation Engineer

Business Line Description:

TEL's new Integrated Circuit Design Solutions (ICDS) team is seeking a layout automation engineer to implement cutting-edge ICs in the latest advanced-node technologies. This engineer will be responsible for creating custom layout and automating tasks such as block tiling, GDS manipulation, toplevel chip construction, and physical verification signoff. Successful candidates have experience in advanced-node layout design and are comfortable creating automation scripts with Python and TCL.

Job Summary:

  • Lay out custom circuit blocks in advanced nodes
  • Perform block-level DRC and LVS
  • Create custom block views (LEF, LIB, etc) to be used by PD team
  • Work with PD team to define interfaces between custom blocks and digital blocks
  • Automate block-level layout tasks such as block tiling
  • Automate GDS manipulation tasks
  • Write scripts to fix systematic DRC errors
  • Automate toplevel chip finishing tasks such as GDS merging
  • Perform toplevel DRC and LVS

Job Qualifications:

  • B.S. (or equivalent) in Electrical Engineering or Computer Engineering required
  • B.S. with 5+ years or M.S. desired
  • Experience creating custom mixed-signal layouts in advanced nodes required
  • Experience with backend EDA tools required
    • Custom layout: Virtuoso, Custom Compiler
    • Physical verification: Calibre, ICValidator
    • GDS manipulation: Calibre DRV, ICV Workbench
  • Good understanding of Python and TCL scripting languages required
  • Experience with other EDA tools desired
    • Synthesis: Genus, Design Compiler
    • Static timing analysis: Primetime, Certus
    • Physical design: Innovus, ICCII
  • Experience with scientific Python libraries (numpy, pandas, matplotlib, etc) desired
  • Excellent verbal and written communication skills

Onsite Job Location:

  • Austin, TX

Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.

Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.

SubsidiaryTOKYO ELECTRON AMERICA, INC.

Top Skills

Python
Tcl
The Company
2,914 Employees
On-site Workplace
Year Founded: 1963

What We Do

Since its founding in 1963, TEL has grown to encompass many offices around the world that engineer, manufacture, sell, and service wafer-processing or semiconductor production equipment (SPE), as well as flat panel display (FPD) and thin-film silicon photovoltaic equipment (PVE). As the world market share leader in several product lines, TEL plays a key role in the evolving global semiconductor industry.

Follow us on Twitter @TokyoElectronUS

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