ASIC Design Engineer - Clocks

Posted 3 Days Ago
Be an Early Applicant
Bengaluru, Bengaluru Urban, Karnataka
Senior level
Artificial Intelligence • Hardware • Robotics • Software • Metaverse
The Role
As an ASIC Design Engineer, you will micro-architect and design clock modules for SOCs, balance frequency and power optimizations, collaborate across SOC functions, automate RTL generation, and engage in the full SOC execution cycle including design sign-off and silicon bringup.
Summary Generated by Built In

NVIDIA Clocks and Resets group is looking for a top ASIC engineer with extensive experience in high-speed logic design and gate-level design implementation and optimization! The complexity of clocking structure has grown significantly over years with increased focus on performance and power. Modern clocking designs need to balance high frequency clocks with power optimizations, DFT, crosstalk, routing and other physical implementation and timing closure constraints. We need a dedicated and motivated engineer to work on next generation Clocking implementation for Tegra SOCs.

What you'll be doing:

  • Micro-architect and Design new clocks modules and topologies in order to support all IPs constituting the SOC.

  • Understand and evaluate the trade-offs across DFX, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.

  • Collaborate with multiple other SOC functions for SOC Clocking Implementation.

  • Working on automation and methodology aspects to generate Clocking RTL in most efficient and scalable way.

  • Get involved in end-to-end cycle of SOC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup!

  • Get exposure to CDC, RDC, Lint, Synthesis, multi-power-domain designs and latest methodologies.

What we need to see:

  • B.Tech or M.Tech in Electronics/VLSI or equivalent experience, with 6+ years of relevant industry work experience

  • Experience in RTL design (Verilog), Gate-level Design and Synthesis

  • Strong coding skills in Perl or other industry-standard scripting languages

  • Excellent interpersonal skills and ability to work with multiple teams to brainstorm optimally.

  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks is a plus.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Verilog
The Company
HQ: Santa Clara, CA
21,960 Employees
On-site Workplace
Year Founded: 1993

What We Do

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, NVIDIA is increasingly known as “the AI computing company.”

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