The Principal Engineer will focus on developing and optimizing models for generative AI applications, including speech recognition and natural language processing. Responsibilities include developing new algorithms, implementing features, mentoring team members, and ensuring seamless software integration across NVIDIA's platforms.

The Senior ASIC Physical Design Engineer will focus on the physical design of CPUs, GPUs, and SoCs, ensuring timing convergence, managing timing constraints, and conducting netlist-related checks such as equivalence and asynchronous checks. The role requires expertise in the full design flow from RTL to tapeout and strong experience with industry-standard EDA tools and scripting languages.

As a Silicon Reliability Engineer, you will oversee the qualification of GPU and SoC systems, perform reliability testing, build automation scripts, and collaborate with multi-functional teams to analyze silicon aging and debug issues. Your role will involve both hardware and software validation, as well as contributing to system-level testing and debugging.

The Technical Support Engineer will provide comprehensive support for Linux-based cluster management software, facilitate collaboration with development teams, conduct research and development, and become a subject-matter expert in various areas. They will assist customers with their cluster management and ensure the successful deployment of NVIDIA technologies.

The role involves providing Tier 1 support for complex cloud platforms, troubleshooting customer issues, documenting solutions, and collaborating with engineering teams. Responsibilities include bug reporting, tool building for customer support, understanding user workloads, and participating in on-call rotations for production systems.

The Senior Software Architect will create proofs-of-concept, develop middleware for AI and HPC, enhance compiler features, and research hardware features for high-performance and data-intensive workloads. The role involves close collaboration in a dynamic environment.

The AI Networking Software Developer will design and implement features for AI communication middleware and networking libraries to enhance performance, resiliency, and scalability. Responsibilities include developing features for libraries and deep learning frameworks, creating proofs-of-concept, and working in a multi-national corporate environment.

The Senior Applied Power Architect - GPU will invent methodologies for power estimation models/tools for GPU products, analyze power vs performance to assist in product decisions, and collaborate with system architects and product engineers on energy efficiency improvements. A strong background in energy-efficient systems and industry experience is required.

The Senior Mask Design Engineer will perform physical layout design for SRAM and datapath circuits using Cadence tools, collaborate with circuit engineers on layout methodologies, and develop verification flows for new technologies. The role requires expertise in layout implementation and strong interpersonal skills for teamwork.

Intern will collaborate with team to develop machine learning policies, implement code on robotic hardware, and improve algorithms for control and manipulation in robotics systems.

As a DFT Engineer, you will work on the verification of state-of-the-art Memory BIST logic, develop robust test plans, perform pre-silicon simulation and debugging, and collaborate closely with design and QA teams to enhance test coverage and software quality.

As a Software Engineer on the Chip Design CAD team, you will develop innovative software solutions and improve existing tools for electrical engineers designing SoCs and Switches. Collaboration with designers and specialists is key to successfully completing your tasks.

As a Physical Design Engineer at NVIDIA, you will be responsible for the physical design of chips, including synthesis, power distribution, timing closure, and verification, while addressing challenges in power, area, and performance. You will collaborate within a professional team to innovate high-speed communication devices.

The Senior Manager will lead the Networking Interconnect Product Engineering team, overseeing Mass Production and Failure Analysis. Responsibilities include team management, production strategy implementation, hardware testing, and quality assurance, alongside collaboration with global teams to enhance production effectiveness.

The role involves performing advanced Static Timing Analysis (STA) for chiplet and Full Chip projects, running Prime Time tests, debugging timing paths, and ensuring project convergence across teams. The engineer will be responsible for timing closure and quality approval from the pre-layout stage to signoff.

Manage and mentor a team focused on Power Optimization within the Physical Design sector, overseeing chip development. Responsibilities include project definition, methodology development, and ensuring optimizations across multiple product lines.

As a Data Engineer at NVIDIA, you'll build data platforms for advanced log analysis, design ELT pipelines, maintain data integrity, and ensure performance across databases, also collaborating with data scientists and stakeholders to optimize server manufacturing processes.

As an ASIC Verification Engineer, you will own ASIC verification tasks for complex IP/Cluster designs in RTL, work with various teams to ensure software testing, create regression plans, perform pre-silicon validation, and debug issues in the post-silicon phase.

The Senior Manager leads the Hardware Engineering team in developing high-speed optical transceivers for NVIDIA's data centers. Responsibilities include team building, project management, and collaboration across various disciplines to drive design and execution of innovative optical interconnects from concept to production while ensuring timely delivery and meeting technical specifications.

NVIDIA is seeking a Senior Physical Design Power Optimization Engineer to optimize power in physical design, handling all chip development aspects from RTL to GDS. The role involves collaboration with various teams and developing methodologies for power optimization. Candidates should have extensive experience in physical design and power optimization.