Application Engineer I - Formal Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Formal Verification Application Engineer I to work with us in Belo Horizonte, Brazil.

As an Application Engineer I , you will be trained to become an expert in Formal Verification methodologies in the System Verification Group Technical Field Operations group (TFO-SVG) in Belo Horizonte. The TFO-SVG group works with Jasper, Xcelium, Palladium, Protium, VIPs, and other Cadence Digital Functional Verification tools. The application engineers provide technical support, enabling customers to effectively deploy our industry-leading technology, focused on RTL-level verification products. You will be in a Formal Verification focused team working with our Jasper Formal Verification Platform and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovative solutions to address the industry most challenging problems.

Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.

Job description:

• Application Engineer on areas listed above reporting to higher management

• Engage with AE team on Pre-sales technical campaigns from the technical side, working along with Sales and Marketing

• Provide technical support to customers and field personnel in RTL verification solutions focused in Jasper (Formal Verification)

• Conduct root cause analysis and provide resolution to customer technical issues

• Run customer test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.

• Close collaboration with R&D on issues using established protocols.

• Author application notes and help provide feedback on documentation

• Use scripting languages like TCL and Python for flow development, automation and enhancing design methodologies

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Minimum Requirements

• Complete Bachelor in Electrical Engineering, Control and Automation Engineering, Systems Engineering, Computer Science and related areas

• Excellent verbal and written communications skills in Portuguese and English

• Good problem-solving skills

• Strong inter-personal and communication skills

• A strong interest in contributing to customer success with related technical interest in EDA, hardware development (HDL's), and Logic Design

Nice to have Skills

• Experience in scripting languages such as TCL and Python is a plus

• Exposure to RTL (Verilog or VHDL)

• Knowledge of Formal Methods is a plus

• Exposure to microelectronics and or EDA, with experience on verification methodologies as formal verification, functional verification (simulation), or model verification. Knowledge of Cadence verification tools is a plus

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Additional Job Details:

• Employment category: CLT

• Employment term: 40 hours/week

• Competitive benefits

• Hybrid work in Belo Horizonte, Minas Gerais, Brazil: Av. do Contorno 5800

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

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