Design next-generation DRAM architecture, lead performance analysis, collaborate with teams, and optimize power efficiency in memory products.

Responsible for working on emulator platforms for Advanced Memory controllers. Duties include improving capabilities, debugging, and maintaining emulation environments while collaborating with cross-functional teams on chip pre-silicon validation.

Research various parallel algorithms for AI inference in distributed environments focusing on performance benchmarking and optimization of large-scale systems.

Develop firmware for embedded memory technologies, analyze requirements, design software architecture, implement software, conduct testing, and optimize performance.

The role involves developing verification environments, creating verification plans, generating test cases, and building auto verification flows for storage controllers in SOC design.

The Staff Engineer will design SoC architectures, implement logic designs, and analyze power consumption for storage solutions, collaborating with various teams to ensure technical specifications are met.

Lead the development of high-performance CPU architecture, mentor a team, drive continuous improvement, and contribute to technical strategy.

The SOC Static Timing Analysis Engineer enhances SSD capabilities by developing prototypes, optimizing for mass production, and collaborating with design teams to ensure timing requirements are met.

Lead the development of high-performance CPU architectures and microarchitectures, mentoring cross-functional teams and ensuring alignment with organizational goals.

The role involves architecting next-generation AI systems, leading technical directions, and solving bottlenecks in memory, compute, and networking for improved performance.

As a Staff ASIC designer, you will design customized HBM buffer die solutions, collaborate with engineering teams, and manage low-power designs, ensuring performance and functionality in semiconductor products.

The performance engineer will develop automation and analysis tools for performance testing of distributed storage systems, including database solutions and dashboards.

Responsible for technical support in the memory applications sector, troubleshooting issues, conducting validations, and working with lab equipment to analyze memory products.

The Senior Staff Engineer will lead DRAM failure mode analysis and develop solutions to enhance memory fault management, collaborating with customers and standardizing logging protocols.

The Contract Administrator will manage contract lifecycle, process requests, support the legal department, and handle invoices while ensuring efficiency and compliance.

Provide operational support to VPs, manage complex travel arrangements, handle internal communications, and coordinate events. Must be bilingual in Korean and English.

As a Test Engineer, drive quality improvements by validating NVMe firmware, analyzing test coverage, deploying tools, and monitoring quality metrics.

Manage the Customer Qualification team for enterprise SSDs, overseeing qualifications, customer interactions, and test teams, while resolving issues and improving processes.

The Staff Engineer, DRAM Design will develop DRAM architecture, optimize designs and collaborate with cross-functional teams, enhancing Samsung's memory technology.

Verify and validate designs for POCs, architecture test benches, implement verification plans, and collaborate with teams for closure on functional targets.