Technical Staff Engineer - Emulation

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The Architecture Co-Verification team (ACOV) is an exciting, fast-paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry-leading HW emulators (such as Cadence Palladium and Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.

This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system-level co-verification using leading-edge HW emulators and FPGA platforms. It’s a high-visibility role that will develop a wide range of skills and exceptional problem-solving abilities.

Responsibilities could include but are not limited to the following:

• Managing a multi-location, cross functional team of engineers and technicians
• Planning and developing a common test ecosystem across pre/post silicon
• Using Jira to plan and track project tasks and report results
• Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans.
• Utilization of test and defect tracking tools to document and report on verification progress and product quality
• Effectively present technical information to small teams of engineers.

Requirements/Qualifications:

• BS/MS/PhD in degree or higher in Electrical/Electronic Engineering or Computer Engineering
• 10+ years of experience in leading FPGA/ASIC/EDA development, simulation and verification projects.
• 1+ years' experience with one or more serial storage protocols such as PCIe, CXL, NVMe, SAS, SATA.
• In-depth knowledge of CXL protocols.
• Experience working with large scale FPGA solutions
• Thorough understanding of digital design, RTL coding and simulation
• Prior knowledge and experience in HDL languages (Verilog, VHDL and SystemVerilog)
• Working knowledge of C/C++, TCL or Perl/Python languages.
• Excellent verbal and written communicational skills.
• Effective team player, collaborator, and a great motivator for team.
• Ability to work in a multi-location, cross functional team
• Proficiency in lab equipment usage for test and debug
• Microcontroller programming skills are desirable

Desired Skills:

• Cadence infrastructure support and maintenance flows
• Proficient in using Agile methodologies in project management

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is .*