University of Southern California

Senior Research Engineer I

Posted 21 Hours Ago

Be an Early Applicant

Arlington, VA

113K-160K Annually

Mid level

Edtech

The Role

The Senior Research Engineer I will research and develop CAD and EDA tools for FPGA hardware, optimizing testing for FPGAs, characterizing device health, and collaborating with peers. They will contribute to research publications and develop automated hardware testing.

Summary Generated by Built In

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, cybersecurity, and communications technologies. ISI’s 350 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.

*This position is located in Arlington, VA. Hybrid work options are available.*

The Reconfigurable Computing Group (RCG) at ISI is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, reconfigurable architectures, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

RCG staff can be found:

Researching and developing toolsets to map AI algorithms directly to hardware,
Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
Developing cutting-edge reconfigurable architectures,
Utilizing ISI’s MOSIS service to fabricate novel computer architectures.

Our success is based on investing in our staff through a culture centered on:

Learning and idea generation,
Transparent and constructive feedback, and
Continual growth through contributing to research.

We are looking for highly talented, motivated developers to perform research and development in the area of CAD and EDA tools for FPGA hardware. This position will collaborate with a high caliber team to create tools for trusted and assured computing. Develop automated hardware testing to validate functionality of a range of FPGA and eFPGA families and resources. Actively participate in developing techniques and tools to characterize and analyze the health of FPGA devices. This position will participate in research while collaborating with peers within the group and across ISI, and support publishing results in top tier conferences.

Position specific JOB QUALIFICATIONS:

MS or Bachelors and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Strong software development (C++/Java/Python) and hardware design (VHDL/Verilog/System Verilog) experience.
3-5 years of experience using Xilinx, Intel, or Lattice FPGA implementation tools.
Qualified candidates for this position must be willing and eligible to apply for a Top Secret clearance. Eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.

Preferred Job Qualifications:

Experience using or contributing to open-source EDA tools such as Torc, RapidWright, ABC, VPR, VTR, RapidSmith, nextpnr, prjXray.
Demonstrable experience in one of the following topics: FPGA CAD tool algorithms (synthesis, partitioning, mapping, placing, routing), design automation, or hardware trust, assurance, and security.
Experience with software revision control systems such as Git, Mercurial, SVN and CI/CD development workflows.

The annual base salary range for this position is $130,000 - $160,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

The University of Southern California values diversity and is committed to equal opportunity in employment.

Minimum Education:
Bachelor's degree
Minimum Experience:
7 years
Minimum Skills:
MS or Bachelors and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Strong software development (C++/Java/Python) and hardware design (VHDL/Verilog/System Verilog) experience.
3-5 years of experience using Xilinx, Intel, or Lattice FPGA implementation tools.
Qualified candidates for this position must be willing and eligible to apply for a Top Secret clearance. Eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.

USC is a smoke-free environment

USC is an equal opportunity, affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristic protected by law or USC policy. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations, including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance, and with due consideration for patient and student safety. Please refer to the Background Screening Policy Appendix D for specific employment screen implications for the position for which you are applying.

We provide reasonable accommodations to applicants and employees with disabilities. Applicants with questions about access or requiring a reasonable accommodation for any part of the application or hiring process should contact USC Human Resources by phone at (213) 821-8100, or by email at [email protected]. Inquiries will be treated as confidential to the extent permitted by law.