Senior Hardware Engineer - Micro-Architect

Posted 3 Days Ago
Be an Early Applicant
Burlingame, CA
Senior level
Hardware • Machine Learning • Software
The Role
The Senior Hardware Engineer will define processor architecture, implement microarchitecture, optimize power and performance, and contribute to timing closure during the product cycle, while collaborating in a team setting for innovative processor design.
Summary Generated by Built In

Description

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.

Role:

This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.

Requirements
  • Contribute to the definition of the processor architecture by understanding its applications
  • Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
  • Own Power, Performance & Area (PPA) optimization
  • Contribute to timing closure through full product cycle (front end, back-end, tapeout)

Requirements:

  • BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
  • Proficiency in SystemC, SystemVerilog, or Verilog
  • Strong background in computer architecture
  • Knowledge of design techniques for low power digital design
  • Knowledge of VCS & Verilog/C Co-Sim
  • Experience in data-parallel hardware design for high-performance computing
  • Experience in FPGA design is a plus
  • Experience in logic synthesis and performance modeling

Nice to haves:

  • Familiarity with automotive safety (ASIL) standards

Expected Outcomes in 12 months:

  • Independently own a major design block and improve PPA
  • Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack

Package design for customer releases and incorporate customer feedback

Benefits
  • Provide competitive salaries and meaningful equity
  • Provide a politics-free community for the brilliant minds who want to make an immediate impact
  • Provide an opportunity for you to build long term career relationships
  • Foster an environment that allows for lasting personal relationships alongside professional ones

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world’s first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow’s technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

Quadric is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, religion, sex, national origin, sexual orientation, age, citizenship, marital status, or disability.

Top Skills

Systemc
Systemverilog
Verilog
The Company
HQ: Burlingame, CA
38 Employees
On-site Workplace
Year Founded: 2017

What We Do

Quadric has built a unified hardware/software architecture optimized for on-device machine learning inference. Only the Quadric GPNPU (general purpose neural processing unit) delivers high ML inference performance while also running C++ code without forcing the developer to artificially partition application code between two or three different kinds of processors. Quadric's GPNPU is a licensable processor IP core that scales from 1 to 64 TOPs and seamlessly intermixes scalar, vector and matrix code.

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