About Neuralink:
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Team Description:
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Job Responsibilities and Description:
The Physical Design and Verification Engineer will be responsible for leading the team efforts on the functional verification of neural recording and stimulation SoCs, which include low-power processors, digital signal processing, hardware accelerators, and analog/mixed-signal IPs. The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly
Required Qualifications:
- Bachelor of Science (B.S.) degree in computer science or a related field, or equivalent experience
- Minimum 3 years of experience in digital ASIC verification
- Excellence in SystemVerilog
- Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
- Experience with code coverage and regression setup
Preferred Qualifications:
- Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools
- Experience building test benches, testing, and debugging for a complex system-on-chip
- Experience in formal verification
- Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
- Experience with IEEE-1801 (UPF) based design simulation flows
- Experience with low power gate level simulations
- Exposure with low power formal verification flows
- Strong hands-on experience in verification methodologies such as UVM
- Knowledge of ARM/RISC-V processor, AMBA bus
- Knowledge of power aware verification
- Experience with FPGA/emulation
- Experience with lab system bring up, writing diagnostic, and lab debugging
- Experience with build tools such as CMake and Bazel
Expected Compensation:
At Neuralink, your base pay is one part of your total compensation package. The anticipated base salary for this position is expected to be within the below range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training.
California Base Salary Range:
$158,000—$243,000 USD
What We Offer:
Full-time employees are eligible for the following benefits listed below.
- An opportunity to change the world and work with some of the smartest and most talented experts from different fields
- Growth potential; we rapidly advance team members who have an outsized impact
- Excellent medical, dental, and vision insurance through a PPO plan
- Paid holidays
- Commuter benefits
- Meals provided
- Equity + 401(k) plan *Temporary Employees & Interns excluded
- Parental leave *Temporary Employees & Interns excluded
- Flexible time off *Temporary Employees & Interns excluded
Top Skills
What We Do
Neuralink is a team of exceptionally talented people. We are creating the future of brain-machine interfaces: building devices now that will help people with paralysis and inventing new technologies that will expand our abilities, our community, and our world.
Our goal is to build a system with at least two orders of magnitude more communication channels (electrodes) than current clinically-approved devices. This system needs to be safe, it must have fully wireless communication through the skin, and it has to be ready for patients to take home and use on their own. Our device, called the Link, will be able to record from 1024 electrodes and is designed to meet these criteria.
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