Principal Engineer, Digital Verification Engineering

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn.

Employer:                    Analog Devices, Inc.  

Job Title:                     Principal Engineer, Digital Verification Engineering=

Job Requisition:        R245214 

Job Location:             Durham, North Carolina

Job Type:                    Full Time

Rate of Pay:                $150,883.00 to $220,020.00 per Year

Duties:                       

Perform RTL and gate-level simulation debug and analysis. Implement state-of-the-art mixed-signal technology radio-frequency (“RF”) Transceiver chips. Collaborate with design teams and software/firmware development teams to capture the intended operation and configuration of the system. Develop SystemVerilog UVM simulation environments, infrastructure and verification plans at both full chip and lock level. Perform design verification using UVM methodologies. Verify logic circuit functionality by writing test-benches and regression tests at both full chip level and block level. Develop system-level test cases using ARM and/or RISC-V processors. Create, simulate and debug constrained random and directed cases based on the verification plans. Create verification IP and enhance verification methodologies. Write functional coverage, simulation assertions, formal assertions, and other metrics to track progress and completeness of verification effort. Conduct regressions analyses, including debugging of circuit failures in regression testing. Run structural simulations with post-layout timing information. Measure and analyze coverage results and take necessary actions to fill the coverage gaps.
Partial telecommute permitted (2 days/week WFH).

Requirements:                 

Must have a Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering or a related field (willing to accept a foreign education equivalent) and 5 years of experience as a Verification Engineer or related occupation managing verification cycle of high-speed protocols using UVM based test benches.

Must also possess the following (quantitative experience requirements not applicable to this section):

• Demonstrated Expertise (DE) architecting and debugging Universal Verification Methodology (UVM) test benches, writing simulation and formal assertions, and debugging Register Transfer Level (RTL), structural, and Standard Delay Format (SDF) gate level simulations;
• DE using tools such as Certitude, Jasper Formal Property Verifier (FPV) and code and functional coverage closure using Cadence vManager;
• DE performing verification of radio-frequency transceiver chips using SystemVerilog and UVM methodology, developing verification plans for block and full chip level verification, and planning and conducting verification reviews;
• DE identifying and integrating internal and third party Intellectual Property (IP) and Verification IP (SystemVerilog and UVM) across multiple sites; and
• DE in SystemVerilog’s interaction with SystemC and C/MATLAB, high speed serial protocols such as JESD, Ethernet and PCIe, and deciphering multi-AMBA protocol (AHB/AXI/APB) bus architected systems.

Contact: Eligible for Employee referral program. Contact: Apply online at https://www.analog.com/en/careers.html and reference job R245214 .

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: Experienced

Required Travel: No

Shift Type: 1st Shift/Days