Principal Engineer - Design

Posted 3 Days Ago
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Burnaby, BC
86K-186K Annually
Senior level
Hardware • Semiconductor
The Role
As a Principal Engineer-Design at Microchip, you'll lead the design of complex digital integrated circuits for the PCIe Switch product line. Your responsibilities include defining subsystem features, supporting ASIC validation, and communicating technical details within a multi-location team. Experience in RTL design and knowledge of complex ASIC flows is essential.
Summary Generated by Built In

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Microchip’s Data Center Solutions (DCS) Business Unit offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Principal Engineer-Design, you will provide leadership in the highly successful PCIe Switch product line. These complex 800M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments.
As a Principal Engineer-Design , your job will entail the following:

  • Design of complex digital integrated circuits at the block, subsystem or device level (100K to 50M+ gates), which are coded in Verilog, System Verilog

  • Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents

  • Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds

  • Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems

  • Communicate with architects to justify design implementation decisions and associated trade-offs

  • Read and understand applicable storage and computer interface protocol standards

Requirements/Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent

  • 8+ years related experience

  • RTL Design - Experience in RTL Design using System Verilog, Verilog is required. 

  • Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control

  • Experience with Formal Verification a plus.

  • Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.

  • Scripting and programming skills using csh, bash, perl, python, tcl, etc. 

  • Protocol knowledge and experience in PCI-Express will be an asset

  • Knowledge of AHB/AXI bus protocols is desired.

  • Excellent knowledge in logic synthesis and static timing analysis.

  • Experience in designing the chip top level with IOs, pin out and package design

  • Worked with physical design teams for layout implementation. Familiar with low power methodology and flows.

  • Capable of debugging EDA tool issues or design related issues.

  • Working knowledge of DFT. 

  • Excellent analytical and debugging skills and the ability to proactively solve issues

  • Good verbal and written communication skills in English will be an asset

  • Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $86,000-$186,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Top Skills

System Verilog
Verilog
The Company
HQ: Chandler, AZ
13,393 Employees
On-site Workplace
Year Founded: 1989

What We Do

Microchip Technology Inc. is a leading semiconductor supplier of smart, connected and secure embedded control solutions. Its easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs which reduce risk while lowering total system cost and time to market.

The company’s solutions serve more than 125,000 customers across the industrial, automotive, consumer, aerospace and defense, communications and computing markets.

Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.

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