Staff Design Verification Engineer

About us:

Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions. 

Role Overview:

As a senior member of the SOC Verification team, you will be responsible for verifying new breeds of SoC for advanced perception applications utilizing 4-D Lidar. You will architect and develop verification environments and verify complex SoC designs using state-of-art verification techniques.

What you'll be doing:

• Lead and drive block, subsystems, and full-chip verification of advanced ARM-based SOCs. 
• Architect and build test benches, reference models, and scoreboard using SystemVerilog and UVM-constrained random methodologies 
• Define and execute test plan for block, subsystem, and full-chip using SV/UVM and C/C++ FW running on the on-chip ARM processors 
• Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define and enhance the processes, methodology, and tools to verify complex SoCs.
• Work with Architects, design and Verification leads, and System software teams to define system-level verification plans and prove that SOC meets the functional, performance, and power target defined in the architecture and design specs. 
• Identify and write functional coverage groups to improve test/stimulus quality
• Analyze Code, Functional, and test plan coverages to identify verification gaps and achieve 100% coverage closure
• Work with the different stakeholders and cross-functional leads to ensure high-quality SoC delivery on time

What you'll have:

• 10+ years of experience in the design, verification, and validation of advanced ARM-based SOCs
• 5+ years in architecting and building constrained random verification environments, reference models, scoreboards and directed self-checking tests using SystemVerilog and UVM methodologies
• Deep understanding of ARM-based SOC verification. Writing assembly and C/C++ diagnostic firmware for embedded ARM processors and debugging in the simulation environment
• Working experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, high-speed serdes, etc.
• Solid programming skills in SystemVerilog, UVM, C/C++, assembly, Perl/Python.
• Proficient in debugging complex SOC or CPU core designs
• Ability to collaborate deeply with cross-functional leads and management teams
• Ability to deliver results in a very fast-moving environmentDesire to learn & implement groundbreaking new processes and methodology for continuous verification improvement

Nice to haves:

• Diagnostics Firmware development and validation experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu 
• Post-silicon bring-up and validation planning and execution

What's in it for you:

• Be part of a fast-paced and dynamic team
• Very competitive compensation and meaningful stock grants
• Exceptional benefits: Medical, Dental, Vision, and more
• Unlimited PTO: We care about results, not punching time cards