Design Verification (DV) Engineer

Posted 2 Days Ago
Be an Early Applicant
Boulder, CO
Junior
Artificial Intelligence • Fintech • Other • Automation
The Role
Design Verification Engineers at HRT are responsible for creating testbenches, writing verification plans, debugging RTL bugs, and managing test suites. They collaborate with designers and improve both open-source and proprietary tools within a fast-paced environment.
Summary Generated by Built In

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

  • Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
  • Writing detailed verification plans
  • Quickly root-cause RTL bugs
  • Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
  • Managing test suites and continuous integration infrastructure
  • Developing and improving open-source and internal tools

Qualifications 

  • Superb debug and analytical skills 
  • Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
  • Experience with code and functional coverage collection/analysis
  • Experience with SystemVerilog and industry-standard frameworks such as UVM
  • Experience with Python
  • Comfortable in a Linux environment
  • Familiarity with Verilator and/or Cocotb preferred
  • C++ experience is a plus
  • A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

Annual base salary range of $175,000 to $225,000. Pay (base and bonus) may vary depending on job-related skills and experience. A sign-on and discretionary performance bonus may be provided as part of the total compensation package, in addition to company-paid medical and/or other benefits.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Culture

Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We’re a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization—from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we’re friends and colleagues – whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we’d love to get to know you.

Top Skills

C++
Python
Systemverilog
The Company
HQ: New York, NY
1,000 Employees
Hybrid Workplace
Year Founded: 2002

What We Do

Hudson River Trading brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.

Why Work With Us

At HRT we are mathematicians, computer scientists, statisticians, physicists and engineers. We believe that by cultivating an environment that encourages idea sharing and collaboration, we develop our best strategies. We boast a flat management structure as all our people are motivated by being at the forefront of the automated trading world.

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Hudson River Trading Offices

Hybrid Workspace

Employees engage in a combination of remote and on-site work.

Teams have a range of in-office needs: some require 24/7 coverage or hands-on maintenance, while others operate across time zones. While the majority of teams adopt a fairly even split between in-office and remote work, many come in every day.

Typical time on-site: Flexible
HQNew York, NY
Singapore
IE
Austin, TX
Boulder, CO
Chicago, IL
London, GB
Learn more

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