AI Hardware Systems Engineer, Principal

Posted 21 Hours Ago
Be an Early Applicant
Santa Clara, CA
Senior level
Artificial Intelligence • Machine Learning • Software
The Role
Design, develop, and deploy GenAI inference solutions, collaborate with cross-functional teams to integrate custom components, lead testing and validation of AI systems, and document processes while staying current with advancements in hardware and software technologies.
Summary Generated by Built In

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Location:

Hybrid, working onsite 3 days per week at our Santa Clara, Ca location.

AI Hardware System Design Engineer

What You Will Do:

· Design, develop, and deploy scalable GenAI inference solutions with d-Matrix accelerator silicon

· Collaborate with cross-functional teams such as chip design, verification, thermal, mechanical and software engineers to specify, design, and integrate custom accelerators, processors, memory modules, and other components required for AI workloads

· Lead the bring-up of new AI systems, conducting prototype testing and validation. Debug and resolve hardware-software integration issues

· Prepare comprehensive documentation and support the transfer of knowledge to internal and external stakeholders

· Stay abreast of the latest advancements in GenAI hardware and software technologies and assess their suitability for integration into d-Matrix GenAI inference solutions

What You Will Bring:

· BS EE or CE - MSEE desired with 10+ years’ experience in hardware development

· Experience in deploying products to volume production

· Hands-on experience in the design, bring up and debug of PCBAs and chassis

· Experience prototyping, reworking, troubleshooting board & component level issues to resolution

· Experience using schematic capture and PCB layout tools

· Working knowledge of Thermal and Mechanical designs

· Familiarity with signal and power integrity concepts

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Top Skills

Genai Inference Solutions
Mechanical Design
Pcb Design
Pcb Layout
Schematic Capture
Thermal Design
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The Company
HQ: Santa Clara, CA
102 Employees
On-site Workplace

What We Do

d-Matrix is building a new way of doing datacenter AI inferencing using in-memory computing (IMC) techniques with chiplet level scale-out interconnects. Founded in 2019, d-Matrix has attacked the physics of memory-compute integration using innovative circuit techniques, ML tools, software and algorithms; solving the memory-compute integration problem, which is the final frontier in AI compute efficiency.

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