As a Staff Software Engineer, you will work on the productization team focusing on large-scale AI solutions, collaborating with cross-functional teams to develop scaleout solutions, and delivering orchestration software. You will also interact with hardware to validate solutions and address customer needs, driving innovative hardware-software integration.

The Neural Network Optimization Engineer develops and optimizes neural networks for AI inference on cutting-edge hardware, collaborates with cross-functional teams, diagnoses user challenges, and ensures effective product usage by customers. They manage projects, communicate optimizations, and engage with customers post-sale, contributing feedback to improve the technology.

The Staff Silicon Characterization Engineer will design experiments to define production operating points of silicon, analyze data, recommend chip binning strategies, and collaborate with product and validation teams to optimize performance, power, and yield.

The Senior Staff Design Verification Engineer will verify new hardware blocks and sub-systems, develop and maintain verification environments, and collaborate with design engineers to meet project goals. Responsibilities include creating test cases and ensuring designs meet performance requirements.

The Staff Emulation & FPGA Prototyping Engineer will utilize FPGA-based platforms and hardware emulation systems to validate pre-silicon designs. Responsibilities include developing prototypes, debugging FPGA implementations, configuring emulation systems, and enabling early software development. The role requires collaboration with design and firmware teams to ensure functionality and performance of system-on-chip designs.

The Technical Program Manager will oversee software engineering programs, define project milestones, track metrics, and manage resources. The role includes coordinating with engineering teams, addressing issues, and establishing best practices in project management.

As a Staff RTL Design Engineer, you will architect, implement, and verify custom hardware designs, focusing on SOCs with advanced interfaces. Responsibilities include designing RTL modules using Verilog/SystemVerilog, simulating hardware testing, and applying Agile methodologies for development, with a strong emphasis on teamwork and problem-solving.

As a Senior/Staff Formal Verification Engineer at Untether AI, you will lead formal verification efforts for Custom-AI hardware designs, collaborating with engineers to ensure accuracy and optimize designs. Responsibilities include developing verification plans, debugging results, and enhancing methodologies in the intersection of AI and hardware.

As a Staff ASIC Design Engineer, you will design, implement, verify, and productize custom hardware designs for ASICs and FPGAs. Responsibilities include designing and coding RTL modules, simulating hardware, performing hardware testing, and applying Agile methodologies.

The Technical Program Manager (TPM) will work closely with stakeholders to drive machine learning silicon and hardware programs towards success. They will define and manage project milestones, track project metrics, anticipate and detect issues, and update stakeholders on project status. The TPM will also coordinate with engineering management to forecast resource loads, develop the project management function, and drive suppliers. They should have 7+ years of experience in hardware development and a post-secondary education in electrical engineering, computer science, or a related field.

As a Staff Pre-Silicon Firmware Engineer, you'll develop low-level embedded firmware, influence architecture, create firmware interfaces, and verify routines pre-silicon. You'll also validate and debug chips in the lab and collaborate with cross-functional teams. Your role includes mentoring engineers and enhancing design tools.

As a Compiler Engineer at Untether AI, you'll develop software to map neural networks onto their hardware, implement data layout strategies, and collaborate with hardware design teams to optimize performance. Your work will focus on creating efficient translations of neural networks for accelerated implementations, addressing functional and performance challenges.