Search the 21 jobs at MIPS

The Staff/Senior Staff Engineer will lead the pre-silicon functional verification of cache coherency in CPU designs. Responsibilities include owning verification environments, implementing best practices for robust verification, and resolving functional and performance issues prior to silicon production. A strong grasp of computer architecture and proficiency in relevant programming languages is essential for success.

Lead a team in developing baremetal and RTOS software for RISC-V CPUs, mentor members, design CPU firmware, optimize software using emulators and hardware, and improve RISC-V CPU cores through collaboration with architecture teams.

The Sr. Staff/Lead Engineer will lead a team in developing Linux software for RISC-V CPUs/Platforms, design and implement software for Linux kernel and device drivers, contribute to open-source projects, analyze and optimize software using emulators, and collaborate with hardware teams for architectural improvements while maintaining documentation and SDK releases.

The Sr. Staff Design Engineer will lead RTL development for high-performance SoC modules, addressing integration, performance, power, and area. Responsibilities include microarchitecture specification, design verification support, RTL refinement for targeted goals, and collaboration with engineering teams for physical design validation.

The Sr. CPU Verification Engineer will oversee the verification closure of CPU blocks or features, utilizing various verification methodologies and tools while collaborating with CPU designers. Key responsibilities include creating functional test plans and leveraging strong programming and analytical skills to ensure high quality CPU designs.

The Sr Staff Trace Design Engineer will lead the RTL development of Debug micro-architecture, drive design of Trace IPs, develop specifications, refine RTL designs, support functional verification, and collaborate with engineering teams on physical design aspects.

The MMU Design Engineer role involves designing and implementing Memory Management Unit architectures for RISC-V CPUs. Responsibilities include developing translation lookaside buffers, collaborating with CPU design teams, preparing documentation, and innovating techniques for enhanced memory management.

The Senior Staff Verification Engineer will own CPU verification from start to finish, collaborating with designers to develop functional test plans. Responsibilities include developing tests in C and SystemVerilog, enhancing verification environments, and working with EDA tools for SOC verification.

The Floating Point Datapath Microarchitect will lead and own the RTL development of a Floating-Point Unit, focusing on performance, power, and area. Responsibilities include designing high-performance arithmetic and logical operations, collaborating with engineering teams, and ensuring functional verification and design goals are met.

The Embedded Software Engineer will design and implement software for RISC-V-based CPUs and platforms, focusing on Linux kernel support, device drivers, and benchmarking. Responsibilities include upstream contributions to open-source projects, optimizing software for performance, and collaborating with hardware teams for enhancements.

Design and implement software for RISC-V-based CPUs/Platforms, including bootloaders and RTOS ports. Contribute to the RISC-V software ecosystem, analyze and optimize software, and work closely with architecture and hardware design teams. Release SDKs and assist customers with prototyping. Requires strong experience in embedded software development with proficiency in C/C++ and knowledge of RTOS.

The Design Implementation Engineer will manage the backend implementation of RISC-V cores, focusing on synthesis, place and route, and timing closure. Responsibilities include UPF-based low-power design, scan insertion, and collaboration with RTL designers to achieve design closure and optimization of performance, power, and area.

The Design Implementation Lead will oversee the backend implementation of RISC-V cores and uncore blocks, focusing on optimizing performance, power, and area (PPA). Mentoring junior team members and leading design methodology improvements are also key responsibilities.

The CPU Verification Engineer will implement functional tests for CPU verification, develop test plans, and stress micro-architectural implementations. This role involves collaboration with designers and debugging across teams, focusing on enhancing the verification environment and using leading verification methodologies.

The Staff Engineer - Full Stack Developer will lead the development of a cloud application for product configuration and customer support in the semiconductor industry, managing end-to-end software processes and ensuring high-quality performance. Responsibilities include designing front-end applications, building secure back-end services, integrating APIs, optimizing databases, and enhancing application capabilities in collaboration with cross-functional teams.

As a Staff Engineer - DevOps, you will manage the automation of software development processes, ensuring quality and security in product delivery. Your responsibilities include containerizing microservices, implementing CI/CD procedures, and monitoring infrastructure, collaborating with development and security teams. Experience in cloud platforms and delivering software at scale is essential.

The Senior Design Verification Engineer will drive verification efforts to closure, develop functional test plans, create and implement directed tests, and analyze coverage for CPU designs. The role involves collaboration with CPU designers and enhancing the testing environment using modern methodologies and tools.

The Sr Staff Trace Design Engineer will lead RTL development for Trace unit design, including micro-architecture specifications and functional verification, while collaborating on physical design aspects. Strong knowledge in SOC debug architecture and experience in designing RISC-V or similar CPUs is desired.

The MMU Design Engineer role involves designing and implementing MMU architectures for RISC-V CPUs, optimizing memory access, collaborating with CPU design teams, preparing documentation, and staying updated on industry trends related to memory management and RISC-V design.

The role involves leading the RTL development for high-performance Floating-Point Units, focusing on design specifications, performance optimization, and collaborating with engineering teams for functional verification. Additional responsibilities include microarchitecture research, configuration of design features, and refining RTL design targets.