The Senior DFT Design Engineer will develop and implement advanced DFT strategies for complex ASICs and SoCs to ensure high-quality silicon production. Responsibilities include integrating and validating manufacturing tests, performing post-silicon validation, optimizing test times, and mentoring junior engineers. This role requires collaboration with cross-functional teams throughout the design and production process.

As a Senior Firmware Architect, you will lead the architecture and development lifecycle of an AI platform using Celestial AI's Photonic Fabric. Responsibilities include defining firmware architecture and APIs, collaborating with hardware and software teams, participating in requirements gathering, and ensuring code quality through reviews and documentation.

The Senior ASIC/VLSI Synthesis and Design Engineer will develop high-performance, low-power digital designs for ASICs and SoCs, focusing on optimizing power, performance, and area, ensuring timing closure, and conducting post-silicon validation. This role includes collaboration with cross-functional teams, implementing synthesis methodologies, and performing power analysis.

The Senior Firmware Engineer at Celestial AI will lead the development of production-grade firmware for their photonic fabric products and collaborate with hardware and software teams to implement communication link management software, ensuring high-quality software delivery while engaging in design, testing, and documentation.

As a Chiplet Design Verification Lead, you'll oversee verification strategy and execution for complex IP, manage a team of verification engineers, and collaborate with architects and design teams to ensure successful product releases. Your responsibilities include defining verification plans and leading the verification of a complex 5nm SoC with high-speed interfaces.

The SoC Design Verification Lead will lead the verification strategy and execution for complex 5nm SoCs, collaborating with architects and design engineers, reviewing verification test plans, and mentoring a team of engineers. This role is crucial for ensuring successful product releases and first-pass tapeout success.

The Photonics Layout Engineer will design layouts for Silicon Photonic chips and contribute to their delivery from floor-planning to verification. The engineer will collaborate with analog, digital, and packaging teams to ensure design meets product requirements, while optimizing layout flows and enhancing design automation.

The Principal Engineer will drive the development of advanced semiconductor packaging technologies for AI products from concept to high volume manufacturing. Responsibilities include collaborating with foundries and OSATs, managing qualification processes, and pursuing innovative packaging solutions while ensuring reliability and cost-effectiveness.

The AMS Design Engineer will lead the development of high-speed analog architecture tailored for AI applications. Responsibilities include conducting architectural analysis, enhancing system performance using advanced analog techniques, defining design specifications, and collaborating with other engineering domains to achieve optimal performance in AMS systems.

The Senior Software Engineer will develop production-grade firmware for Celestial AI's photonic fabric products, collaborating on AI/ML solutions. Responsibilities include requirements gathering, software design, code review, and communication link management software development.

The Compiler Engineer will expand backend functionality and optimizations for Celestial AI's Machine Learning accelerator. Responsibilities include design and improvement of compiler performance, output analysis, and collaboration with hardware teams to enhance architecture and software compilers.

The Principal Engineer will lead high-performance analog design for transceivers, collaborating with cross-functional teams to architect and validate circuits. Responsibilities include designing SerDes, guiding layout engineering, and interfacing with customers.

The Mixed-Signal Verification Engineer will focus on modeling, simulation, and validation of mixed-signal ASICs, bridging the analog and digital domains. Responsibilities include developing simulation environments, collaborating with design teams, analyzing performance, creating test plans, automating workflows, and supporting silicon validation.