Search the 12 jobs at Celestial AI

The Compiler Engineer will expand backend functionality and optimizations for Celestial AI's Machine Learning accelerator. Responsibilities include design and improvement of compiler performance, output analysis, and collaboration with hardware teams to enhance architecture and software compilers.

The Principal Engineer will lead high-performance analog design for transceivers, collaborating with cross-functional teams to architect and validate circuits. Responsibilities include designing SerDes, guiding layout engineering, and interfacing with customers.

The Mixed Signal Verification Engineer will develop and maintain simulation environments for mixed-signal ASICs, collaborating with design teams to model critical components, analyze system-level performance, create simulation test plans, and correlate simulation results with lab measurements.

As a Senior Technical Writer at Celestial AI, you will be responsible for driving the development and implementation of technical content strategies, creating and maintaining documentation such as user guides and white papers, and ensuring the accuracy and clarity of technical information. You will collaborate with engineers and product managers to convey complex concepts.

As a Chiplet Design Verification Lead, you will oversee verification strategies for complex 5nm SoCs, lead a team of verification engineers, manage project milestones, and collaborate with architects and design teams to ensure successful product releases. You will also enhance verification methodologies and processes while ensuring first-pass tapeout success.

The SoC Design Verification Lead will oversee SoC verification efforts from pre-silicon to production, collaborating with architects, customers, and engineers, while managing a team of verification engineers. The role involves defining verification plans, shaping methodologies, and ensuring successful product releases through effective milestone management.

The Photonics Layout Engineer will be an essential member of the Physical Design team, focusing on the layout of Silicon Photonic chips. Responsibilities include contributing to the design and verification of Photonic ICs, collaborating with various teams to ensure product performance, and optimizing layout processes using specific design tools.

The Principal Engineer will drive AI product development from concept to high volume manufacturing, focusing on 2.5D and 3D packaging technologies. Responsibilities include managing assembly processes, qualification of packaging, and collaborating with foundries and OSATs, while managing risks and ensuring design for manufacturing.

The Senior ASIC/VLSI Synthesis and Design Engineer will develop complex digital designs for high-performance ASICs/SoCs. Responsibilities include optimizing design for power, performance, and area, performing timing closure, gate level simulation, and power analysis, and collaborating with design teams. The candidate will also implement DFT flows and address design issues through various methodologies.

The RTL Design Engineer will design and implement custom RTL modules for the Celestial SoC, focusing on low power consumption and high-quality reusable designs. Responsibilities include authoring design specifications, collaborating with DV engineers, evaluating performance tradeoffs, and driving coverage closure for designs.

The AMS Design Engineer will develop high-speed analog architecture tailored for AI applications. Responsibilities include top-down analysis of AMS systems, designing low-power analog circuits, defining specifications, and collaborating with multiple engineers.

As a Senior Software Engineer at Celestial AI, you will develop production-grade firmware for AI solutions using Photonic Fabric technology. Your role involves gathering requirements, implementing communication software, and collaborating closely with hardware/software teams, as well as ensuring high-quality output through best practices in software development.