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11 Days Ago
Burlingame, CA, USA
38 Employees
Expert/Leader
38 Employees
Expert/Leader
Hardware • Machine Learning • Software
In this role, you will lead the platform software engineering team, overseeing the development of SDK front end APIs, managing product roadmaps, and ensuring the deployment of processes for quality software development and validation.
11 Days Ago
Burlingame, CA, USA
38 Employees
Senior level
38 Employees
Senior level
Hardware • Machine Learning • Software
The FPGA Engineer will lead the development of prototyping platforms, focusing on FPGA and HAPS systems. Responsibilities include developing hardware verification tests, building regression environments, and debugging issues prior to escalation. The role requires hands-on experience with implementing FPGA systems and collaborating across teams to optimize products.
11 Days Ago
Burlingame, CA, USA
38 Employees
Senior level
38 Employees
Senior level
Hardware • Machine Learning • Software
As a Senior Hardware Engineer, you will contribute to the design cycle of a revolutionary new general purpose neural processing unit (GPNPU), including defining processor architecture, implementing RTL in SystemC or SystemVerilog, and optimizing Power, Performance, and Area (PPA). You will work on timing closure and build an understanding of SW interfaces to debug issues within the HW stack.
11 Days Ago
Burlingame, CA, USA
38 Employees
Senior level
38 Employees
Senior level
Hardware • Machine Learning • Software
Join Quadric as a Senior Design Verification Engineer to architect and develop test benches for GPNPU processors. Collaborate with architects and designers to document verification plans, implement testbenches with commercial tools, and communicate verification progress through coverage metrics.
11 Days Ago
Burlingame, CA, USA
38 Employees
Senior level
38 Employees
Senior level
Hardware • Machine Learning • Software
As a Physical Design Methodology Engineer, you will develop design methodologies and automation scripts for processor IP implementation, collaborate with architecture teams to optimize performance, and perform test chip tape outs across multiple process nodes.
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