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Design state-of-the-art DDR memory controllers for various applications, architect solutions for DDR controller features, and collaborate with project teams to enhance development processes and productivity.
As a Principal Product Engineer at Cadence, you will work closely with R&D and engineering teams to enhance advanced chip design tools. Your responsibilities include characterizing IP, analyzing various Liberty formats, conducting customer engagement, running benchmarks, and developing automation using scripting languages.
As a Product Engineering Architect at Cadence, you will debug customer simulation issues, define specifications for new features, work with R&D on implementations, maintain test case suites, and support product documentation and customer training.
As a Software Engineer II in the VIP team at Cadence, you'll develop software for emulating communication protocols. This role requires strong software development skills, engagement with customers, and knowledge of relevant protocols and tools in a collaborative environment.
RTL Design Engineer for DDR Memory Controller IP development team, responsible for designing and supporting the RTL of DDR Memory Controller solution, working on existing RTL, adding new features, supporting customers, and ensuring design guidelines are met.
The Lead Software Engineer at Cadence will design and develop software programs related to physical and routing processes, collaborate with a global R&D team, and provide engineering solutions to enhance customer success. A strong background in problem solving, C/C++ development in a Linux environment, and knowledge of data structures and algorithms is essential.
You will enhance and expand existing EDA tools' architecture, create frameworks for analysis of advanced circuit effects, and utilize machine learning to improve speed and usability of solutions. As a member of the R&D team, your work will focus on transistor level analysis for complex digital and mixed-signal circuits.
3+ years of ASIC Design/Verification experience in PCIe/Storage domain. Strong expertise in ONFI, XSPI, SD/eMMC. Strong debugging and communication skills.
The Principal Solutions Engineer at Cadence will work with customers to build Virtual/Hybrid prototypes for software development and system validation. Responsibilities include understanding modeling needs, creating and validating system models using C/C++/SystemC, integrating into larger systems, and assisting with debugging and custom tool flows. This role allows opportunities for technical growth and collaboration within a diverse team.
The Principal Software Engineer at Cadence is responsible for driving innovations in electronic design automation (EDA), with a focus on emulation. The role involves leveraging strong skills in C++ and SystemVerilog, along with protocol knowledge, particularly in MIPI protocols, to develop impactful technological solutions.
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