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The Scale-out Engineer will design and maintain the TT-fabric networking library for AI processors, develop distributed training systems for deep learning, optimize communication for AI clusters, and collaborate with AI model builders and researchers to enhance scale-out infrastructure.

As a Software Engineer specializing in AI Compilers, you will design, develop, and optimize compilers for advanced semiconductor products, working collaboratively with engineers to enhance performance of machine learning applications and integrate software into leading frameworks.

The Staff Design Verification Engineer will create verification plans and develop DV environments primarily using System Verilog and UVM methodologies. Responsibilities include executing test plans, performing functional verification at the RTL level, and developing Universal Verification Components. Candidates must have a Bachelor's or Master's degree in relevant fields and experience in DV and verification methodologies.