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The Staff Engineer I - Physical Design will handle physical design and verification tasks for ASIC development, including floor-planning, timing closure, and IR/EM analysis. The role involves mentoring junior team members and ensuring the integration of different design components. Reporting to the ASIC Design Director, the engineer will work in a hybrid environment managing project-specific workflows.

As a Staff Engineer I for RTL Design, you will lead architecture proposals, manage design teams, and ensure delivery on various key projects aligning with ARM architecture and IP integration, while overseeing progress with cross-functional teams.

Responsible for the verification of IP, Block, or Subsystem at SoC Level, including generating documentation, debugging, and developing verification environments. Requires expertise in digital verification methodologies and protocols.