Sr. Principal Design verification engineer

Posted 9 Days Ago
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Austin, TX
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The role involves leading design verification for modules, guiding the creation of impactful knowledge content, and providing technical leadership to a small team. Responsibilities include solving complex problems, mentoring, and delivering quality results within schedule requirements while utilizing specialized domain knowledge.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities
 
Become a PoC for assigned module and deliver high quality TB and Testcases to Cadence customers
Provides a proactive and creative approach to resolving problems using specialized domain knowledge
Guides creation and publishing of high quality and impactful knowledge content in SOCDV/IPDV as per Customer Requirements
Provides effective technical leadership and mentoring for a small team working at Cadence to deliver quality results according to schedule requirements
Solves highly complex problems and is able to identify viable and often innovative options, and uses analytical skills and judgment to recommend an appropriate solution
 
Qualifications
 
Bachelor’s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 15 years related experience
OR Masters 12 years of related experience
OR PhD 10 years of related experience
 
Experience and Technical Skills required
 
> Minimum 10 years of experience in Processor based full chip verification / IP Verification
Knowledge of Verilog/System Verilog, digital simulation and debug
Knowledge of HS/LS Protocols / Processor based SOC architecture and digital design fundamentals
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology / formal / Power Aware Simulations / GLS
Experience with C/C++. Debugging disassembly assembly is a plus
Experience with RTL to Post Silicon Validation DV methodologies/flows is a plus
Experience with perl, python or similar scripting language is a plus
Expert level experience with multiple industry standard tools usage (preferably Cadence tools),
Ability to analyze customer's environment and evaluate appropriate solutions; able to architect flows; anticipates technical issues and develops creative solutions before they become a problem
Ability to work independently, must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
 
Behavioral skills required
Must possess strong written, verbal and presentation skills
Ability to establish a close working relationship with both customer peers and management
Explore what’s possible to get the job done, including creative use of unconventional solutions
Work effectively across functions and geographies
Push to raise the bar while always operating with integrity

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Verilog,System Verilog,C,C++,Perl,Python
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The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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