Senior Mask Layout Design Engineer

Posted 9 Days Ago
Be an Early Applicant
Santa Clara, CA
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The Role
The Senior Mask Layout Design Engineer will perform physical layout for mixed-signal circuits using Cadence tools, collaborate with ASIC engineers, and manage design verification for sub-micron CMOS technologies. Responsibilities include floor planning, layout customization, and debugging using verification tools.
Summary Generated by Built In

Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing:

  • Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools

  • You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products and Job duties will include floor planning, custom layout and verifying against design rules and schematics.

What we need to see:

  • Hold a BSEE or equivalent experience. MSEE is a plus.

  • 8+ years of relevant mask design / layout experience

  • Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.

  • Experience with high-speed SerDes/RF layout design is helpful and Experience with top level integration would be excellent to have.

  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies

  • Validated experience with Cadence custom circuit design tools - particularly virtuoso

  • Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre

  • Ability to work optimally in a team, good interpersonal skills and positive energy.

  • Proficiency in scripting languages like perl, python, skill etc. is a plus

  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks

The base salary range is 124,000 USD - 230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Cadence
Perl
Python
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The Company
HQ: Santa Clara, CA
21,960 Employees
On-site Workplace
Year Founded: 1993

What We Do

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, NVIDIA is increasingly known as “the AI computing company.”

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